Simulation Results: clkmgr

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.96 %
  • code
  • 97.47 %
  • assert
  • 93.50 %
  • func
  • 84.91 %
  • line
  • 98.76 %
  • branch
  • 98.17 %
  • cond
  • 91.41 %
  • toggle
  • 99.03 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.920s 28.456us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 1.000s 146.424us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.900s 31.984us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.500s 287.526us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.140s 60.783us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.890s 52.140us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.900s 31.984us 1 1 100.00
clkmgr_csr_aliasing 1.140s 60.783us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.910s 41.648us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.910s 507.623us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.730s 34.284us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.650s 14.266us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.920s 28.456us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 10.370s 2116.502us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 1.670s 537.114us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 10.370s 2116.502us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 14.990s 3745.339us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.810s 57.277us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.330s 220.147us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.330s 220.147us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 1.000s 146.424us 1 1 100.00
clkmgr_csr_rw 0.900s 31.984us 1 1 100.00
clkmgr_csr_aliasing 1.140s 60.783us 1 1 100.00
clkmgr_same_csr_outstanding 0.910s 96.382us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 1.000s 146.424us 1 1 100.00
clkmgr_csr_rw 0.900s 31.984us 1 1 100.00
clkmgr_csr_aliasing 1.140s 60.783us 1 1 100.00
clkmgr_same_csr_outstanding 0.910s 96.382us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 36.640s 10014.478us 0 1 0.00
clkmgr_tl_intg_err 22.700s 10039.996us 0 1 0.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 450.500s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 450.500s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 450.500s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 450.500s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.380s 61.914us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 22.700s 10039.996us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 10.370s 2116.502us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 1.670s 537.114us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 450.500s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.840s 37.238us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.870s 105.059us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.980s 24.636us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.810s 20.618us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.890s 75.689us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.900s 31.984us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 36.640s 10014.478us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.900s 31.984us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.900s 31.984us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 36.640s 10014.478us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.830s 1418.976us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 70.250s 11953.446us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 2 test runs
clkmgr_sec_cm 66054181033763120829545984339370501489998286325889290698492808811158670155368 84
UVM_INFO @ 10014478096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 14185980788839517674942458058489557360864633649107759879979171794246567235783 97
UVM_INFO @ 10039995562 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 113705166494897921204481790647294498733567470000421061880541782115418583817384 75
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---