Simulation Results: csrng

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 77.29 %
  • code
  • 90.34 %
  • assert
  • 93.01 %
  • func
  • 48.53 %
  • block
  • 95.05 %
  • line
  • 95.81 %
  • branch
  • 88.14 %
  • toggle
  • 91.68 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
83.33%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 1.000s 24.045us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 94.817us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 44.576us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 59.000s 6164.293us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 21.360us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 71.226us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 44.576us 1 1 100.00
csrng_csr_aliasing 2.000s 21.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 6.000s 278.372us 1 1 100.00
alerts 1 1 100.00
csrng_alert 10.000s 608.848us 1 1 100.00
err 1 1 100.00
csrng_err 1.000s 26.707us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 5.000s 288.143us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 5.000s 288.143us 0 1 0.00
stress_all 0 1 0.00
csrng_stress_all 144.000s 5508.307us 0 1 0.00
intr_test 1 1 100.00
csrng_intr_test 3.000s 22.943us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 17.468us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 8.000s 477.333us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 8.000s 477.333us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 94.817us 1 1 100.00
csrng_csr_rw 2.000s 44.576us 1 1 100.00
csrng_csr_aliasing 2.000s 21.360us 1 1 100.00
csrng_same_csr_outstanding 2.000s 35.795us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 94.817us 1 1 100.00
csrng_csr_rw 2.000s 44.576us 1 1 100.00
csrng_csr_aliasing 2.000s 21.360us 1 1 100.00
csrng_same_csr_outstanding 2.000s 35.795us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 5.000s 242.582us 1 1 100.00
csrng_tl_intg_err 10.000s 1140.960us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 1.000s 23.238us 1 1 100.00
csrng_csr_rw 2.000s 44.576us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 10.000s 608.848us 1 1 100.00
sec_cm_intersig_mubi 0 1 0.00
csrng_stress_all 144.000s 5508.307us 0 1 0.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 6.000s 278.372us 1 1 100.00
csrng_err 1.000s 26.707us 1 1 100.00
csrng_sec_cm 5.000s 242.582us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 6.000s 278.372us 1 1 100.00
csrng_err 1.000s 26.707us 1 1 100.00
csrng_sec_cm 5.000s 242.582us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 6.000s 278.372us 1 1 100.00
csrng_err 1.000s 26.707us 1 1 100.00
csrng_sec_cm 5.000s 242.582us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 6.000s 278.372us 1 1 100.00
csrng_err 1.000s 26.707us 1 1 100.00
csrng_sec_cm 5.000s 242.582us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 6.000s 278.372us 1 1 100.00
csrng_err 1.000s 26.707us 1 1 100.00
csrng_sec_cm 5.000s 242.582us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 10.000s 608.848us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 6.000s 278.372us 1 1 100.00
csrng_err 1.000s 26.707us 1 1 100.00
sec_cm_constants_lc_gated 0 1 0.00
csrng_stress_all 144.000s 5508.307us 0 1 0.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 10.000s 608.848us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 10.000s 1140.960us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 6.000s 278.372us 1 1 100.00
csrng_err 1.000s 26.707us 1 1 100.00
csrng_sec_cm 5.000s 242.582us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 6.000s 278.372us 1 1 100.00
csrng_err 1.000s 26.707us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 6.000s 278.372us 1 1 100.00
csrng_err 1.000s 26.707us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 6.000s 278.372us 1 1 100.00
csrng_err 1.000s 26.707us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 6.000s 278.372us 1 1 100.00
csrng_err 1.000s 26.707us 1 1 100.00
csrng_sec_cm 5.000s 242.582us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 6.000s 278.372us 1 1 100.00
csrng_err 1.000s 26.707us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.271s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 15548459015300074854164432529564444389448715548748041255423327491324989834871 100
UVM_INFO @ 288142760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csrng_scoreboard.sv:177) [scoreboard] Check failed intr_pins[i] === (intr_en[i] & item.d_data[i]) (* [*] vs * [*]) Interrupt_pin: EntropyReq 1 test run
csrng_stress_all 85635301273041183726626209531698880883223776356553598160298572654720851664181 104
UVM_INFO @ 5508306798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 42109849823001593325007274769370169382159546956308481092700276438988283711622 None