Simulation Results: edn/edn1

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.09 %
  • code
  • 83.99 %
  • assert
  • 98.70 %
  • func
  • 78.57 %
  • line
  • 98.25 %
  • branch
  • 93.72 %
  • cond
  • 88.85 %
  • toggle
  • 94.80 %
  • FSM
  • 44.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.830s 18.213us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.080s 65.333us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.740s 18.649us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.280s 2003.620us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.350s 46.084us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.130s 284.612us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.740s 18.649us 1 1 100.00
edn_csr_aliasing 1.350s 46.084us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.100s 54.333us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.100s 54.333us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.100s 54.333us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.740s 26.351us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.930s 42.827us 1 1 100.00
errs 1 1 100.00
edn_err 0.840s 21.729us 1 1 100.00
disable 2 2 100.00
edn_disable 0.820s 17.672us 1 1 100.00
edn_disable_auto_req_mode 1.090s 39.281us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.250s 292.259us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.730s 55.334us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.830s 15.536us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.020s 352.558us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.020s 352.558us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.080s 65.333us 1 1 100.00
edn_csr_rw 0.740s 18.649us 1 1 100.00
edn_csr_aliasing 1.350s 46.084us 1 1 100.00
edn_same_csr_outstanding 0.800s 18.213us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.080s 65.333us 1 1 100.00
edn_csr_rw 0.740s 18.649us 1 1 100.00
edn_csr_aliasing 1.350s 46.084us 1 1 100.00
edn_same_csr_outstanding 0.800s 18.213us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.120s 167.087us 1 1 100.00
edn_tl_intg_err 1.660s 80.748us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.790s 36.082us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.930s 42.827us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.120s 167.087us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.120s 167.087us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.120s 167.087us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.120s 167.087us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.930s 42.827us 1 1 100.00
edn_sec_cm 2.120s 167.087us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.930s 42.827us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.660s 80.748us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 15.600s 1883.767us 1 1 100.00