Simulation Results: entropy_src/rng_4bits

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.70 %
  • code
  • 87.25 %
  • assert
  • 84.24 %
  • func
  • 49.62 %
  • block
  • 94.32 %
  • line
  • 97.01 %
  • branch
  • 86.31 %
  • toggle
  • 76.10 %
  • FSM
  • 89.58 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 1.000s 103.686us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 19.636us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 21.214us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 7.000s 1858.769us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 106.417us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 5.097us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 21.214us 1 1 100.00
entropy_src_csr_aliasing 3.000s 106.417us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 1.000s 103.686us 1 1 100.00
entropy_src_rng 187.000s 13017.038us 1 1 100.00
entropy_src_fw_ov 51.000s 14111.252us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 51.000s 14111.252us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 187.000s 13017.038us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 45.000s 13152.787us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 187.000s 13017.038us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 187.000s 13017.038us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 187.000s 13017.038us 1 1 100.00
entropy_src_intr 2.000s 45.015us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 187.000s 13017.038us 1 1 100.00
entropy_src_functional_alerts 4.000s 976.571us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 220.000s 14255.672us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 58.475us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 30.998us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 60.263us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 38.809us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 384.970us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 384.970us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 19.636us 1 1 100.00
entropy_src_csr_rw 1.000s 21.214us 1 1 100.00
entropy_src_csr_aliasing 3.000s 106.417us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 74.615us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 19.636us 1 1 100.00
entropy_src_csr_rw 1.000s 21.214us 1 1 100.00
entropy_src_csr_aliasing 3.000s 106.417us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 74.615us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 168.139us 1 1 100.00
entropy_src_tl_intg_err 2.000s 60.793us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 187.000s 13017.038us 1 1 100.00
entropy_src_cfg_regwen 2.000s 14.494us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 187.000s 13017.038us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 187.000s 13017.038us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 187.000s 13017.038us 1 1 100.00
entropy_src_fw_ov 51.000s 14111.252us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 58.475us 1 1 100.00
entropy_src_sec_cm 2.000s 168.139us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 58.475us 1 1 100.00
entropy_src_sec_cm 2.000s 168.139us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 187.000s 13017.038us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 58.475us 1 1 100.00
entropy_src_sec_cm 2.000s 168.139us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 58.475us 1 1 100.00
entropy_src_sec_cm 2.000s 168.139us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 58.475us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 976.571us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 2.000s 60.793us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 207.000s 14055.456us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 15.000s 941.536us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 96628321814371672948310809709743449650311043543984325391104093848114217766154 828
UVM_INFO @ 941535650 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror alert_fail_counts 1 test run
entropy_src_csr_mem_rw_with_rand_reset 84959318285608808303353106038566222488296204510161978458615818264280173546497 113
UVM_INFO @ 5097455 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---