Simulation Results: flash_ctrl

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.59 %
  • code
  • 94.02 %
  • assert
  • 97.02 %
  • func
  • 95.73 %
  • line
  • 95.98 %
  • branch
  • 97.10 %
  • cond
  • 93.86 %
  • toggle
  • 98.12 %
  • FSM
  • 85.03 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 63.540s 20.673us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 13.460s 19.136us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 21.390s 191.853us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 9.190s 98.351us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 37.620s 15062.922us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 17.610s 224.977us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.970s 78.547us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 9.190s 98.351us 1 1 100.00
flash_ctrl_csr_aliasing 17.610s 224.977us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 10.570s 17.765us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 12.690s 32.887us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 13.510s 23.836us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 43.900s 130.064us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1138.100s 106764.423us 1 1 100.00
flash_ctrl_hw_rma_reset 664.870s 480419.740us 1 1 100.00
flash_ctrl_lcmgr_intg 11.300s 23.036us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1430.860s 251819.680us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 207.830s 5423.094us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.710s 65.693us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2109.240s 54187.122us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 71.850s 10120.036us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.600s 202.611us 1 1 100.00
flash_ctrl_rw_evict_all_en 15.620s 71.509us 1 1 100.00
flash_ctrl_re_evict 16.450s 79.975us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 103.770s 1402.853us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 103.770s 1402.853us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 261.230s 17148.197us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 10.960s 115.939us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 281.780s 196.328us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 355.930s 5506.558us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 301.640s 2024.460us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 735.070s 413.190us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.390s 80.348us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 140.330s 1518.716us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.140s 71.124us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.730s 28.368us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 534.900s 527.755us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 93.730s 8232.336us 1 1 100.00
flash_ctrl_otp_reset 60.070s 41.767us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1138.100s 106764.423us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 80.950s 513.575us 1 1 100.00
flash_ctrl_intr_wr 47.660s 2568.055us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 192.370s 51367.215us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 411.090s 527806.609us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 47.440s 4539.452us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 39.470s 2824.054us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 13.060s 29.746us 1 1 100.00
flash_ctrl_ro_derr 125.390s 863.023us 1 1 100.00
flash_ctrl_rw_derr 148.300s 6505.927us 1 1 100.00
flash_ctrl_derr_detect 95.990s 1429.121us 1 1 100.00
flash_ctrl_integrity 464.600s 21367.413us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.630s 131.675us 1 1 100.00
flash_ctrl_ro_serr 96.280s 747.184us 1 1 100.00
flash_ctrl_rw_serr 130.530s 28895.929us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 54.580s 3588.547us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 56.910s 1116.136us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 106.430s 5096.358us 1 1 100.00
flash_ctrl_write_word_sweep 7.300s 157.350us 1 1 100.00
flash_ctrl_read_word_sweep 8.080s 30.162us 1 1 100.00
flash_ctrl_ro 89.870s 1641.973us 1 1 100.00
flash_ctrl_rw 348.490s 15941.435us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 28.540s 6818.702us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 570.770s 79171.489us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 27.420s 10069.165us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.870s 49.007us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 7.150s 30.976us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 11.120s 63.786us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 11.120s 63.786us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 21.390s 191.853us 1 1 100.00
flash_ctrl_csr_rw 9.190s 98.351us 1 1 100.00
flash_ctrl_csr_aliasing 17.610s 224.977us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.530s 1437.028us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 21.390s 191.853us 1 1 100.00
flash_ctrl_csr_rw 9.190s 98.351us 1 1 100.00
flash_ctrl_csr_aliasing 17.610s 224.977us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.530s 1437.028us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 25.480s 23.880us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 25.480s 23.880us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 25.480s 23.880us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 25.480s 23.880us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 34.630s 281.165us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1762.790s 4806.630us 1 1 100.00
flash_ctrl_tl_intg_err 314.050s 1477.320us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 314.050s 1477.320us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 314.050s 1477.320us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 17.740s 239.293us 1 1 100.00
flash_ctrl_wr_intg 6.740s 49.853us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 63.540s 20.673us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 60.070s 41.767us 1 1 100.00
flash_ctrl_disable 10.140s 71.124us 1 1 100.00
flash_ctrl_sec_info_access 35.980s 645.525us 1 1 100.00
flash_ctrl_connect 7.730s 28.368us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.120s 189.996us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.190s 98.351us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 25.480s 23.880us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.190s 98.351us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 25.480s 23.880us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 9.190s 98.351us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 25.480s 23.880us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.140s 71.124us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 17.740s 239.293us 1 1 100.00
flash_ctrl_access_after_disable 6.060s 23.784us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 15.340s 103.491us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.140s 71.124us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 10.960s 115.939us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 348.490s 15941.435us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 130.530s 28895.929us 1 1 100.00
flash_ctrl_rw_derr 148.300s 6505.927us 1 1 100.00
flash_ctrl_integrity 464.600s 21367.413us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1138.100s 106764.423us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1762.790s 4806.630us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1762.790s 4806.630us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1762.790s 4806.630us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1762.790s 4806.630us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 11.950s 679.753us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.900s 25.339us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 11.200s 212.780us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1762.790s 4806.630us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1762.790s 4806.630us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1762.790s 4806.630us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.800s 43.575us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 296.260s 4458.034us 1 1 100.00