Simulation Results: hmac

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.31 %
  • code
  • 97.71 %
  • assert
  • 97.60 %
  • func
  • 42.62 %
  • line
  • 99.74 %
  • branch
  • 99.17 %
  • cond
  • 95.73 %
  • toggle
  • 99.77 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 1.150s 124.911us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.850s 116.144us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.940s 92.656us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.280s 463.119us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.280s 219.211us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.260s 70.675us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.940s 92.656us 1 1 100.00
hmac_csr_aliasing 2.280s 219.211us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 20.560s 10101.950us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 84.800s 17888.073us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 203.620s 8872.342us 1 1 100.00
hmac_test_sha384_vectors 379.830s 35125.639us 1 1 100.00
hmac_test_sha512_vectors 381.240s 31327.520us 1 1 100.00
hmac_test_hmac256_vectors 9.800s 375.283us 1 1 100.00
hmac_test_hmac384_vectors 9.910s 3594.166us 1 1 100.00
hmac_test_hmac512_vectors 7.920s 495.033us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 1.890s 61.361us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 729.710s 7526.866us 1 1 100.00
error 1 1 100.00
hmac_error 7.770s 976.102us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 37.140s 2606.309us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 1.150s 124.911us 1 1 100.00
hmac_long_msg 20.560s 10101.950us 1 1 100.00
hmac_back_pressure 84.800s 17888.073us 1 1 100.00
hmac_datapath_stress 729.710s 7526.866us 1 1 100.00
hmac_burst_wr 1.890s 61.361us 1 1 100.00
hmac_stress_all 223.150s 135892.065us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 1.150s 124.911us 1 1 100.00
hmac_long_msg 20.560s 10101.950us 1 1 100.00
hmac_back_pressure 84.800s 17888.073us 1 1 100.00
hmac_datapath_stress 729.710s 7526.866us 1 1 100.00
hmac_wipe_secret 37.140s 2606.309us 1 1 100.00
hmac_test_sha256_vectors 203.620s 8872.342us 1 1 100.00
hmac_test_sha384_vectors 379.830s 35125.639us 1 1 100.00
hmac_test_sha512_vectors 381.240s 31327.520us 1 1 100.00
hmac_test_hmac256_vectors 9.800s 375.283us 1 1 100.00
hmac_test_hmac384_vectors 9.910s 3594.166us 1 1 100.00
hmac_test_hmac512_vectors 7.920s 495.033us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 1.150s 124.911us 1 1 100.00
hmac_long_msg 20.560s 10101.950us 1 1 100.00
hmac_back_pressure 84.800s 17888.073us 1 1 100.00
hmac_datapath_stress 729.710s 7526.866us 1 1 100.00
hmac_burst_wr 1.890s 61.361us 1 1 100.00
hmac_error 7.770s 976.102us 1 1 100.00
hmac_wipe_secret 37.140s 2606.309us 1 1 100.00
hmac_test_sha256_vectors 203.620s 8872.342us 1 1 100.00
hmac_test_sha384_vectors 379.830s 35125.639us 1 1 100.00
hmac_test_sha512_vectors 381.240s 31327.520us 1 1 100.00
hmac_test_hmac256_vectors 9.800s 375.283us 1 1 100.00
hmac_test_hmac384_vectors 9.910s 3594.166us 1 1 100.00
hmac_test_hmac512_vectors 7.920s 495.033us 1 1 100.00
hmac_stress_all 223.150s 135892.065us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 223.150s 135892.065us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.620s 27.100us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.720s 12.141us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.710s 112.108us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.710s 112.108us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.850s 116.144us 1 1 100.00
hmac_csr_rw 0.940s 92.656us 1 1 100.00
hmac_csr_aliasing 2.280s 219.211us 1 1 100.00
hmac_same_csr_outstanding 1.550s 60.907us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.850s 116.144us 1 1 100.00
hmac_csr_rw 0.940s 92.656us 1 1 100.00
hmac_csr_aliasing 2.280s 219.211us 1 1 100.00
hmac_same_csr_outstanding 1.550s 60.907us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.140s 66.822us 1 1 100.00
hmac_tl_intg_err 2.430s 100.453us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.430s 100.453us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 1.150s 124.911us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 5.910s 151.142us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 45.250s 1059.805us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.980s 41.252us 1 1 100.00