Simulation Results

Simulation Results: i2c

14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.69 %

code
82.02 %

assert
97.25 %

func
77.80 %

line
96.57 %

branch
92.76 %

cond
86.13 %

toggle
88.82 %

FSM
45.83 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	35.980s	5798.854us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	7.370s	1577.477us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.870s	26.335us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.890s	202.833us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.160s	655.044us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.130s	454.470us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.830s	27.128us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.890s	202.833us	1	1	100.00
	i2c_csr_aliasing	1.130s	454.470us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				1	1	100.00
	i2c_host_error_intr	3.220s	1104.051us	1	1	100.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	3602.227s	0.000us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	17.110s	13839.056us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.780s	31.295us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	72.490s	5270.648us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	97.500s	11865.014us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.850s	87.072us	1	1	100.00
	i2c_host_fifo_fmt_empty	6.830s	589.872us	1	1	100.00
	i2c_host_fifo_reset_rx	3.990s	495.216us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	41.830s	2327.010us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	13.120s	2521.011us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.810s	31.767us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.750s	854.280us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	28.140s	107640.788us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.870s	2248.882us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	8.410s	638.544us	1	1	100.00
	i2c_target_intr_smoke	3.570s	1629.830us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.930s	158.247us	1	1	100.00
	i2c_target_fifo_reset_tx	1.580s	680.967us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	30.290s	54928.956us	1	1	100.00
	i2c_target_stress_rd	8.410s	638.544us	1	1	100.00
	i2c_target_intr_stress_wr	62.090s	19383.813us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.000s	1498.766us	1	1	100.00
target_clock_stretch				0	1	0.00
	i2c_target_stretch	5.930s	10025.954us	0	1	0.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.740s	1276.481us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	12.150s	10267.813us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.460s	2780.971us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.160s	464.491us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	17.110s	13839.056us	1	1	100.00
	i2c_host_perf_precise	19.990s	6561.555us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	13.120s	2521.011us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.340s	168.439us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.160s	467.589us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.280s	6023.547us	1	1	100.00
	i2c_target_nack_txstretch	1.550s	471.316us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	10.910s	1479.799us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	2.300s	2044.206us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.720s	29.199us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.930s	16.538us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.490s	302.916us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.490s	302.916us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.870s	26.335us	1	1	100.00
	i2c_csr_rw	0.890s	202.833us	1	1	100.00
	i2c_csr_aliasing	1.130s	454.470us	1	1	100.00
	i2c_same_csr_outstanding	0.920s	60.377us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.870s	26.335us	1	1	100.00
	i2c_csr_rw	0.890s	202.833us	1	1	100.00
	i2c_csr_aliasing	1.130s	454.470us	1	1	100.00
	i2c_same_csr_outstanding	0.920s	60.377us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.580s	155.409us	1	1	100.00
	i2c_sec_cm	0.970s	126.593us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.580s	155.409us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	52.860s	3567.892us	1
target_error_intr				1
	i2c_target_unexp_stop	1.150s	54.365us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	7.790s	1364.200us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	25099403147105731253931277773357579255061995208699867460279092104411904250860	112	UVM_INFO @ 3567892306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	17201432990917562227254837440112482194482989059658013470850988586529506971550	90	UVM_INFO @ 1364199560 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	i2c_host_stress_all	23170025270305938219881640115396098528298422086220843066810536391270094817365	None
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	90011419755501956103300193684777075007665094542369318131580299343300661352803	84	UVM_INFO @ 854280009 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_base_vseq.sv:759) [process_txq] wait timeout occurred!				1 test run
	i2c_target_stretch	108122566205468728542524905888018528232635976660783042058458844028592925167644	78	UVM_INFO @ 10025954484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	7367492999266921236801449545429920374167143704241687161509588865173028249573	78	UVM_INFO @ 54364586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	35771980792542838520963626756929626521618423098462297583055791932382642769077	79	UVM_INFO @ 10267812683 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				1 test run
	i2c_host_mode_toggle	56879401655681749176290004412640044572313979619296589184416914831256211482867	81	UVM_INFO @ 31767453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---