Simulation Results: keymgr

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.43 %
  • code
  • 93.13 %
  • assert
  • 97.49 %
  • func
  • 53.66 %
  • line
  • 98.60 %
  • branch
  • 97.35 %
  • cond
  • 93.60 %
  • toggle
  • 92.38 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.670s 72.508us 1 1 100.00
random 1 1 100.00
keymgr_random 5.530s 413.685us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.230s 77.815us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.090s 13.002us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 26.880s 1438.573us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 5.380s 500.556us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.410s 506.151us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.090s 13.002us 1 1 100.00
keymgr_csr_aliasing 5.380s 500.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 13.850s 2694.818us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 4.170s 671.831us 1 1 100.00
keymgr_sideload_kmac 4.260s 99.760us 1 1 100.00
keymgr_sideload_aes 5.110s 1800.219us 1 1 100.00
keymgr_sideload_otbn 2.130s 26.426us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 6.030s 296.472us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 4.250s 188.763us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.470s 50.718us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 2.960s 59.571us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 4.550s 1229.635us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.940s 79.981us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 8.200s 1129.430us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.920s 16.305us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.950s 51.563us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.640s 133.871us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.640s 133.871us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.230s 77.815us 1 1 100.00
keymgr_csr_rw 1.090s 13.002us 1 1 100.00
keymgr_csr_aliasing 5.380s 500.556us 1 1 100.00
keymgr_same_csr_outstanding 2.140s 89.223us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.230s 77.815us 1 1 100.00
keymgr_csr_rw 1.090s 13.002us 1 1 100.00
keymgr_csr_aliasing 5.380s 500.556us 1 1 100.00
keymgr_same_csr_outstanding 2.140s 89.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 7.390s 979.165us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 7.390s 979.165us 1 1 100.00
keymgr_tl_intg_err 2.140s 58.466us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 3.060s 253.880us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 3.060s 253.880us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 3.060s 253.880us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 3.060s 253.880us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 13.450s 5288.643us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 7.390s 979.165us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 7.390s 979.165us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 2.140s 58.466us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 3.060s 253.880us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 13.850s 2694.818us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 5.530s 413.685us 1 1 100.00
keymgr_csr_rw 1.090s 13.002us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 5.530s 413.685us 1 1 100.00
keymgr_csr_rw 1.090s 13.002us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 5.530s 413.685us 1 1 100.00
keymgr_csr_rw 1.090s 13.002us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 4.250s 188.763us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 4.550s 1229.635us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 4.550s 1229.635us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 5.530s 413.685us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.880s 549.891us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.390s 979.165us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.390s 979.165us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 7.390s 979.165us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 3.010s 192.006us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 4.250s 188.763us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 7.390s 979.165us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.390s 979.165us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 7.390s 979.165us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.010s 192.006us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.010s 192.006us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 7.390s 979.165us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.010s 192.006us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 7.390s 979.165us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 3.010s 192.006us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 3.270s 665.692us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 58008716215451112508086202966316001129108618669282781143947320654280168099722 245
UVM_INFO @ 665691804 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---