Simulation Results: kmac/unmasked

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.16 %
  • code
  • 66.06 %
  • assert
  • 96.50 %
  • func
  • 74.93 %
  • line
  • 92.81 %
  • branch
  • 87.20 %
  • cond
  • 82.55 %
  • toggle
  • 27.58 %
  • FSM
  • 40.15 %
Validation stages
V1
100.00%
V2
72.41%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 42.030s 20335.881us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.930s 94.345us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.010s 23.955us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 11.880s 4636.780us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 4.900s 275.317us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.540s 50.695us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.010s 23.955us 1 1 100.00
kmac_csr_aliasing 4.900s 275.317us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.840s 20.319us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.280s 180.447us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 678.630s 327788.726us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 202.240s 3836.585us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 25.220s 876.071us 1 1 100.00
kmac_test_vectors_sha3_256 1336.260s 26038.782us 1 1 100.00
kmac_test_vectors_sha3_384 905.010s 38722.550us 1 1 100.00
kmac_test_vectors_sha3_512 15.240s 1127.945us 1 1 100.00
kmac_test_vectors_shake_128 1723.660s 33076.695us 1 1 100.00
kmac_test_vectors_shake_256 232.740s 7642.663us 1 1 100.00
kmac_test_vectors_kmac 2.400s 131.581us 1 1 100.00
kmac_test_vectors_kmac_xof 1.920s 151.373us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 72.250s 6897.348us 1 1 100.00
app 0 1 0.00
kmac_app 0.990s 103.071us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 1.320s 321.893us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 1.690s 458.605us 0 1 0.00
error 0 1 0.00
kmac_error 8.600s 2094.979us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 0.800s 39.868us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 0.960s 6.215us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 25.350s 3605.162us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 11.420s 749.391us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 0.800s 31.963us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.410s 70.872us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 0.810s 281.683us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.880s 20.266us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.130s 72.493us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.230s 150.555us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.230s 150.555us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.930s 94.345us 1 1 100.00
kmac_csr_rw 1.010s 23.955us 1 1 100.00
kmac_csr_aliasing 4.900s 275.317us 1 1 100.00
kmac_same_csr_outstanding 1.370s 66.039us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.930s 94.345us 1 1 100.00
kmac_csr_rw 1.010s 23.955us 1 1 100.00
kmac_csr_aliasing 4.900s 275.317us 1 1 100.00
kmac_same_csr_outstanding 1.370s 66.039us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.740s 56.976us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.740s 56.976us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.740s 56.976us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.740s 56.976us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.180s 334.979us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 45.250s 7969.655us 1 1 100.00
kmac_tl_intg_err 2.140s 382.539us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.140s 382.539us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.410s 70.872us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 42.030s 20335.881us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 72.250s 6897.348us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.740s 56.976us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 45.250s 7969.655us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 45.250s 7969.655us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 45.250s 7969.655us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 42.030s 20335.881us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.410s 70.872us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 45.250s 7969.655us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 1.070s 192.065us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 42.030s 20335.881us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 49.870s 4040.322us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 6 test runs
kmac_app 51833862640793990364428009123950488137526005589246684875878456883809550609114 77
UVM_INFO @ 103070870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 92196969642267051369941576247798393721418958553583739022601930492354470973332 77
UVM_INFO @ 321892607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 36881839929682842556180393280361943541932016788076923492264190285897373421575 77
UVM_INFO @ 458605010 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 32169622258696612122991925140061133101548409164419564026133430421416180749694 81
UVM_INFO @ 2094979357 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 27627734254173208681777898811099094799893830033450745175815270278189059090500 77
UVM_INFO @ 31963106 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 60288391330325305721383791112124484559477673601015980301709486653724725987117 222
UVM_INFO @ 4040322235 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_sideload_invalid 92595772899325218122032186234793953686241083403132815311807919287764437644120 79
UVM_ERROR @ 6215295 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 6215295 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 35158299738247383749917244662823763361351519071876866466468525322465960268086 78
UVM_ERROR @ 39867518 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 39867518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 2 test runs
kmac_mubi 57851569590660889409561353755402042205874287437314321887655579413913478266203 77
UVM_INFO @ 192064789 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 86793740175087620980110037347506391797385205003836339422371759810704990226002 79
UVM_INFO @ 281682793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---