Simulation Results: lc_ctrl/volatile_unlock_disabled

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.26 %
  • code
  • 83.23 %
  • assert
  • 94.13 %
  • func
  • 93.42 %
  • line
  • 97.15 %
  • branch
  • 93.41 %
  • cond
  • 78.94 %
  • toggle
  • 84.02 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.720s 25.180us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.040s 15.887us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.130s 13.605us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.400s 61.555us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.790s 39.183us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.410s 48.029us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.130s 13.605us 1 1 100.00
lc_ctrl_csr_aliasing 1.790s 39.183us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.340s 240.598us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.280s 483.058us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.830s 40.984us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.940s 163.813us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 11.760s 718.936us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.940s 1001.875us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 11.760s 718.936us 1 1 100.00
lc_ctrl_prog_failure 1.940s 163.813us 1 1 100.00
lc_ctrl_errors 5.940s 1001.875us 1 1 100.00
lc_ctrl_security_escalation 6.940s 413.563us 1 1 100.00
lc_ctrl_jtag_state_failure 17.990s 1264.842us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.550s 138.172us 1 1 100.00
lc_ctrl_jtag_errors 23.870s 1142.352us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 10.030s 2196.282us 1 1 100.00
lc_ctrl_jtag_state_post_trans 21.270s 2714.211us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.550s 138.172us 1 1 100.00
lc_ctrl_jtag_errors 23.870s 1142.352us 1 1 100.00
lc_ctrl_jtag_access 3.460s 1294.304us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.160s 4357.016us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.440s 117.997us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.730s 108.531us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 19.830s 10945.855us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.670s 1480.469us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.310s 26.423us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.620s 405.929us 1 1 100.00
lc_ctrl_jtag_alert_test 1.140s 49.715us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.640s 462.956us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.870s 44.218us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 46.720s 52319.408us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.370s 15.954us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.410s 854.083us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.410s 854.083us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.040s 15.887us 1 1 100.00
lc_ctrl_csr_rw 1.130s 13.605us 1 1 100.00
lc_ctrl_csr_aliasing 1.790s 39.183us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.640s 199.866us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.040s 15.887us 1 1 100.00
lc_ctrl_csr_rw 1.130s 13.605us 1 1 100.00
lc_ctrl_csr_aliasing 1.790s 39.183us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.640s 199.866us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.420s 514.930us 1 1 100.00
lc_ctrl_tl_intg_err 1.530s 47.891us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.530s 47.891us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.280s 483.058us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 11.760s 718.936us 1 1 100.00
lc_ctrl_sec_cm 5.420s 514.930us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 11.760s 718.936us 1 1 100.00
lc_ctrl_sec_cm 5.420s 514.930us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.760s 718.936us 1 1 100.00
lc_ctrl_sec_cm 5.420s 514.930us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.760s 718.936us 1 1 100.00
lc_ctrl_sec_cm 5.420s 514.930us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 11.760s 718.936us 1 1 100.00
lc_ctrl_sec_cm 5.420s 514.930us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.760s 718.936us 1 1 100.00
lc_ctrl_sec_cm 5.420s 514.930us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.760s 718.936us 1 1 100.00
lc_ctrl_sec_cm 5.420s 514.930us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 11.760s 718.936us 1 1 100.00
lc_ctrl_sec_cm 5.420s 514.930us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.940s 413.563us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.340s 240.598us 1 1 100.00
lc_ctrl_jtag_state_post_trans 21.270s 2714.211us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.120s 846.343us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.120s 846.343us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.990s 1816.720us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.640s 526.230us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.640s 526.230us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 60.370s 10844.182us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:923) virtual_sequencer [lc_ctrl_common_vseq] Alert fatal_state_error fired unexpectedly. 1 test run
lc_ctrl_stress_all_with_rand_reset 66484960935296586686730551719631771007442783785461782055575736962020904019017 3611
UVM_INFO @ 10844181923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---