Simulation Results: lc_ctrl/volatile_unlock_enabled

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.05 %
  • code
  • 83.11 %
  • assert
  • 94.69 %
  • func
  • 92.35 %
  • line
  • 96.95 %
  • branch
  • 93.08 %
  • cond
  • 78.85 %
  • toggle
  • 84.99 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.350s 41.647us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.980s 150.395us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.030s 15.882us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.160s 44.666us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 94.285us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.570s 256.227us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.030s 15.882us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 94.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.680s 474.122us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.910s 252.618us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.840s 22.005us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.070s 79.077us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.950s 240.047us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.820s 703.965us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.950s 240.047us 1 1 100.00
lc_ctrl_prog_failure 2.070s 79.077us 1 1 100.00
lc_ctrl_errors 4.820s 703.965us 1 1 100.00
lc_ctrl_security_escalation 4.740s 194.085us 1 1 100.00
lc_ctrl_jtag_state_failure 45.850s 3778.709us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.350s 376.162us 1 1 100.00
lc_ctrl_jtag_errors 65.110s 18041.264us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 9.890s 598.659us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.850s 1263.637us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.350s 376.162us 1 1 100.00
lc_ctrl_jtag_errors 65.110s 18041.264us 1 1 100.00
lc_ctrl_jtag_access 2.680s 112.070us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 6.300s 2234.655us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.490s 47.616us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.380s 39.963us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.770s 4948.993us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.480s 364.630us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.110s 181.122us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.480s 74.816us 1 1 100.00
lc_ctrl_jtag_alert_test 1.320s 41.909us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.800s 458.255us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.900s 30.250us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 95.920s 19912.859us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.360s 88.334us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.490s 253.765us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.490s 253.765us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.980s 150.395us 1 1 100.00
lc_ctrl_csr_rw 1.030s 15.882us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 94.285us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.440s 78.976us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.980s 150.395us 1 1 100.00
lc_ctrl_csr_rw 1.030s 15.882us 1 1 100.00
lc_ctrl_csr_aliasing 1.290s 94.285us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.440s 78.976us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.700s 263.315us 1 1 100.00
lc_ctrl_tl_intg_err 2.070s 131.723us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.070s 131.723us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.910s 252.618us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.950s 240.047us 1 1 100.00
lc_ctrl_sec_cm 7.700s 263.315us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.950s 240.047us 1 1 100.00
lc_ctrl_sec_cm 7.700s 263.315us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.950s 240.047us 1 1 100.00
lc_ctrl_sec_cm 7.700s 263.315us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.950s 240.047us 1 1 100.00
lc_ctrl_sec_cm 7.700s 263.315us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.950s 240.047us 1 1 100.00
lc_ctrl_sec_cm 7.700s 263.315us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.950s 240.047us 1 1 100.00
lc_ctrl_sec_cm 7.700s 263.315us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.950s 240.047us 1 1 100.00
lc_ctrl_sec_cm 7.700s 263.315us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.950s 240.047us 1 1 100.00
lc_ctrl_sec_cm 7.700s 263.315us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.740s 194.085us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.680s 474.122us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.850s 1263.637us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.950s 939.827us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.950s 939.827us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.020s 1133.202us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.430s 1281.133us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 10.430s 1281.133us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 1.860s 476.078us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 91627331955154353306213352326584780224161691046608683647969415462239577191347 150
UVM_INFO @ 476077866 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---