Simulation Results: otp_ctrl

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.37 %
  • code
  • 78.99 %
  • assert
  • 94.88 %
  • func
  • 76.25 %
  • line
  • 88.75 %
  • branch
  • 83.64 %
  • cond
  • 90.54 %
  • toggle
  • 86.71 %
  • FSM
  • 45.31 %
Validation stages
V1
88.89%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.620s 207.239us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.510s 153.103us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.990s 94.566us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.430s 46.029us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.750s 2101.313us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 2.310s 83.329us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.300s 107.074us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.430s 46.029us 1 1 100.00
otp_ctrl_csr_aliasing 2.310s 83.329us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.350s 563.798us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.310s 138.933us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.100s 376.324us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.700s 256.869us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 17.330s 2109.908us 1 1 100.00
otp_ctrl_check_fail 15.070s 11157.834us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 9.780s 1298.608us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 15.080s 2920.597us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 10.780s 406.411us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 15.060s 822.110us 1 1 100.00
otp_ctrl_parallel_lc_esc 3.860s 171.984us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 11.270s 1381.398us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 22.170s 3119.387us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 10.050s 2593.414us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 47.890s 38227.509us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.470s 604.242us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.190s 182.098us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.370s 154.689us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.370s 154.689us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.990s 94.566us 1 1 100.00
otp_ctrl_csr_rw 1.430s 46.029us 1 1 100.00
otp_ctrl_csr_aliasing 2.310s 83.329us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.840s 338.545us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.990s 94.566us 1 1 100.00
otp_ctrl_csr_rw 1.430s 46.029us 1 1 100.00
otp_ctrl_csr_aliasing 2.310s 83.329us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.840s 338.545us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
otp_ctrl_tl_intg_err 7.250s 1035.157us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.250s 1035.157us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.510s 153.103us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.510s 153.103us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.860s 171.984us 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.860s 171.984us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.860s 171.984us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.860s 171.984us 1 1 100.00
otp_ctrl_macro_errs 22.170s 3119.387us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.860s 171.984us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.860s 171.984us 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.860s 171.984us 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.860s 171.984us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.860s 171.984us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.860s 171.984us 1 1 100.00
otp_ctrl_macro_errs 22.170s 3119.387us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 3.860s 171.984us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 3.860s 171.984us 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.700s 256.869us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 15.070s 11157.834us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 15.080s 2920.597us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 15.080s 2920.597us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 15.080s 2920.597us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 15.080s 2920.597us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 15.080s 2920.597us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.510s 153.103us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 15.080s 2920.597us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.510s 153.103us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 137.950s 179538.983us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 9.780s 1298.608us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.510s 153.103us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.510s 153.103us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 22.170s 3119.387us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 10.560s 3577.448us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 26.110s 948.860us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:277) [scoreboard] Check failed exp_alert != OtpNoAlert (* [*] vs * [*]) 1 test run
otp_ctrl_stress_all_with_rand_reset 42878182024002745690207263723784873788479694977376892526276068831292930378274 13475
UVM_INFO @ 948859527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_csr_mem_rw_with_rand_reset 24179317622247669430575719602381805260510648473264161901927804980617886974441 92
UVM_INFO @ 107074101 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---