Simulation Results: pwrmgr

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.27 %
  • code
  • 97.34 %
  • assert
  • 98.96 %
  • func
  • 98.52 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.62 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.640s 26.714us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.710s 31.383us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.670s 47.528us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.820s 759.234us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.810s 86.682us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.840s 40.944us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.670s 47.528us 1 1 100.00
pwrmgr_csr_aliasing 0.810s 86.682us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.910s 168.446us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.910s 168.446us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.750s 94.450us 1 1 100.00
pwrmgr_lowpower_invalid 0.690s 69.606us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.900s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.820s 129.215us 1 1 100.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 0.900s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.660s 114.834us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.860s 558.613us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.740s 99.455us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 3.210s 1753.248us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.670s 56.212us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 2.040s 292.016us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 2.040s 292.016us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 31.383us 1 1 100.00
pwrmgr_csr_rw 0.670s 47.528us 1 1 100.00
pwrmgr_csr_aliasing 0.810s 86.682us 1 1 100.00
pwrmgr_same_csr_outstanding 0.730s 263.128us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 31.383us 1 1 100.00
pwrmgr_csr_rw 0.670s 47.528us 1 1 100.00
pwrmgr_csr_aliasing 0.810s 86.682us 1 1 100.00
pwrmgr_same_csr_outstanding 0.730s 263.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.920s 458.520us 1 1 100.00
pwrmgr_sec_cm 1.510s 665.148us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.510s 665.148us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.510s 665.148us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.920s 458.520us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.570s 1007.990us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.660s 114.834us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.730s 1226.809us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.840s 167.400us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.620s 39.712us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.510s 665.148us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.510s 665.148us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.510s 665.148us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.610s 22.960us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.650s 39.717us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.840s 227.418us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.670s 47.528us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.670s 47.528us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.760s 201.073us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 7.970s 8309.185us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 93503420064294074765893386277356315254523933007948685619836270748520507800269 113
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 108115493340446382752946913908909963827351267683281082602874243967570404542988 79
UVM_ERROR @ 201073338 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 201073338 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---