Simulation Results: rom_ctrl/32kb

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.78 %
  • code
  • 98.52 %
  • assert
  • 97.68 %
  • func
  • 97.14 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 97.92 %
  • toggle
  • 95.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.420s 537.572us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.240s 190.721us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.030s 500.014us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 3.940s 141.945us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.600s 124.601us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 3.760s 128.231us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.030s 500.014us 1 1 100.00
rom_ctrl_csr_aliasing 3.600s 124.601us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.680s 127.298us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.370s 220.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 3.430s 348.342us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 13.220s 1598.429us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 8.050s 308.865us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 4.180s 168.884us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.790s 164.199us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.790s 164.199us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.240s 190.721us 1 1 100.00
rom_ctrl_csr_rw 3.030s 500.014us 1 1 100.00
rom_ctrl_csr_aliasing 3.600s 124.601us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.050s 630.940us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.240s 190.721us 1 1 100.00
rom_ctrl_csr_rw 3.030s 500.014us 1 1 100.00
rom_ctrl_csr_aliasing 3.600s 124.601us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.050s 630.940us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.660s 6704.638us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.470s 2802.629us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 218.300s 1273.316us 1 1 100.00
rom_ctrl_tl_intg_err 45.270s 509.106us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 218.300s 1273.316us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 218.300s 1273.316us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.660s 6704.638us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.660s 6704.638us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.660s 6704.638us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.660s 6704.638us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.660s 6704.638us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 218.300s 1273.316us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 218.300s 1273.316us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.420s 537.572us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.420s 537.572us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.420s 537.572us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 45.270s 509.106us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.660s 6704.638us 1 1 100.00
rom_ctrl_kmac_err_chk 8.050s 308.865us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.660s 6704.638us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.660s 6704.638us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 49.660s 6704.638us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 13.470s 2802.629us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 218.300s 1273.316us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 64.230s 5265.515us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 113110064717284595943225809927379400524128320481116586650034466743698650730010 79
UVM_INFO @ 348342233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---