Simulation Results: rom_ctrl/64kb

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.99 %
  • code
  • 98.58 %
  • assert
  • 97.53 %
  • func
  • 97.85 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 98.22 %
  • toggle
  • 95.57 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.010s 744.567us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 9.570s 295.827us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 7.060s 297.251us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 7.030s 452.876us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.290s 1020.618us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.270s 1241.295us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 7.060s 297.251us 1 1 100.00
rom_ctrl_csr_aliasing 7.290s 1020.618us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 8.580s 19668.867us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 8.410s 8994.004us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 7.210s 4118.170us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 20.590s 1678.458us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.970s 394.300us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.860s 656.301us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.430s 698.870us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.430s 698.870us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.570s 295.827us 1 1 100.00
rom_ctrl_csr_rw 7.060s 297.251us 1 1 100.00
rom_ctrl_csr_aliasing 7.290s 1020.618us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.380s 1026.496us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 9.570s 295.827us 1 1 100.00
rom_ctrl_csr_rw 7.060s 297.251us 1 1 100.00
rom_ctrl_csr_aliasing 7.290s 1020.618us 1 1 100.00
rom_ctrl_same_csr_outstanding 6.380s 1026.496us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 211.860s 40325.832us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.310s 1103.459us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 461.110s 1518.115us 1 1 100.00
rom_ctrl_tl_intg_err 104.500s 372.567us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 461.110s 1518.115us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 461.110s 1518.115us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 211.860s 40325.832us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 211.860s 40325.832us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 211.860s 40325.832us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 211.860s 40325.832us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 211.860s 40325.832us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 461.110s 1518.115us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 461.110s 1518.115us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.010s 744.567us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.010s 744.567us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.010s 744.567us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 104.500s 372.567us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 211.860s 40325.832us 1 1 100.00
rom_ctrl_kmac_err_chk 12.970s 394.300us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 211.860s 40325.832us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 211.860s 40325.832us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 211.860s 40325.832us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 27.310s 1103.459us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 461.110s 1518.115us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 88.200s 16611.572us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 47972767144657583588961523033659850019165925243735030337892268240370400649917 79
UVM_INFO @ 4118169748 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---