Simulation Results: rv_timer

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.65 %
  • code
  • 94.46 %
  • assert
  • 98.73 %
  • func
  • 96.76 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 77.85 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.940s 48.193us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.660s 118.067us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.580s 36.682us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.260s 2124.682us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.870s 31.357us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.710s 18.826us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.580s 36.682us 1 1 100.00
rv_timer_csr_aliasing 0.870s 31.357us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 2.360s 7928.009us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 2.430s 2023.559us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 3.600s 3542.434us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 3.600s 3542.434us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 1.930s 3610.756us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.650s 53.055us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.600s 18.969us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.480s 79.186us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.480s 79.186us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.660s 118.067us 1 1 100.00
rv_timer_csr_rw 0.580s 36.682us 1 1 100.00
rv_timer_csr_aliasing 0.870s 31.357us 1 1 100.00
rv_timer_same_csr_outstanding 0.780s 69.484us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.660s 118.067us 1 1 100.00
rv_timer_csr_rw 0.580s 36.682us 1 1 100.00
rv_timer_csr_aliasing 0.870s 31.357us 1 1 100.00
rv_timer_same_csr_outstanding 0.780s 69.484us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.760s 210.834us 1 1 100.00
rv_timer_tl_intg_err 0.930s 89.832us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.930s 89.832us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.830s 225.559us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.660s 173.535us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 25.100s 61942.801us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 87786096289450499201586194131960967182394667641409924759121752132354083955699 75
UVM_INFO @ 225558926 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 53399587609024692994926232025624502035269188431455498602303148484065242627227 77
UVM_INFO @ 7928009037 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 96910419682960303431922656439528597629976074220480429284399990438460751101564 75
UVM_INFO @ 173535226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---