Simulation Results: spi_device/1r1w

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.83 %
  • code
  • 92.95 %
  • assert
  • 95.52 %
  • func
  • 66.02 %
  • line
  • 98.83 %
  • branch
  • 98.09 %
  • cond
  • 95.47 %
  • toggle
  • 83.01 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 22.180s 12648.115us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.830s 41.142us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.700s 37.836us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 25.190s 2777.283us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 6.890s 871.059us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.130s 96.815us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.700s 37.836us 1 1 100.00
spi_device_csr_aliasing 6.890s 871.059us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.870s 34.577us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.410s 25.346us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.780s 20.897us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.960s 2.963us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.910s 4.087us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.250s 73.420us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.250s 73.420us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 2.230s 1534.071us 1 1 100.00
spi_device_tpm_sts_read 0.830s 232.605us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 27.090s 7494.449us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 5.510s 3777.305us 1 1 100.00
spi_device_flash_all 150.110s 39340.991us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.090s 584.406us 1 1 100.00
spi_device_flash_all 150.110s 39340.991us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 3.090s 584.406us 1 1 100.00
spi_device_flash_all 150.110s 39340.991us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 150.110s 39340.991us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 12.010s 9533.380us 1 1 100.00
spi_device_flash_all 150.110s 39340.991us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 12.010s 9533.380us 1 1 100.00
spi_device_flash_all 150.110s 39340.991us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 12.010s 9533.380us 1 1 100.00
spi_device_flash_all 150.110s 39340.991us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 12.010s 9533.380us 1 1 100.00
spi_device_flash_all 150.110s 39340.991us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 12.010s 9533.380us 1 1 100.00
spi_device_flash_all 150.110s 39340.991us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 8.060s 16383.639us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 5.330s 2162.809us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 5.330s 2162.809us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 5.330s 2162.809us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 5.840s 406.300us 1 1 100.00
spi_device_read_buffer_direct 4.000s 1580.616us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 5.330s 2162.809us 1 1 100.00
spi_device_flash_all 150.110s 39340.991us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 150.110s 39340.991us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 150.110s 39340.991us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.550s 303.372us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.550s 303.372us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 8.610s 5485.874us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 22.180s 12648.115us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 49.740s 6717.647us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 339.050s 119431.804us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.690s 100.994us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.780s 38.845us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.150s 51.620us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.150s 51.620us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.830s 41.142us 1 1 100.00
spi_device_csr_rw 1.700s 37.836us 1 1 100.00
spi_device_csr_aliasing 6.890s 871.059us 1 1 100.00
spi_device_same_csr_outstanding 3.230s 182.101us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.830s 41.142us 1 1 100.00
spi_device_csr_rw 1.700s 37.836us 1 1 100.00
spi_device_csr_aliasing 6.890s 871.059us 1 1 100.00
spi_device_same_csr_outstanding 3.230s 182.101us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.110s 93.088us 1 1 100.00
spi_device_tl_intg_err 11.780s 1128.566us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 11.780s 1128.566us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 80272237316346349687910256936983518623478738169003248266760246511241297351173 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 2042745 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 2042745 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[1005])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 16368004784972497608241903378892013422972957267221884378727073922631646861080 76
UVM_ERROR @ 1766155 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6cce98 [11011001100111010011000] vs 0x0 [0])
UVM_ERROR @ 1783155 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb09a0d [101100001001101000001101] vs 0x0 [0])
UVM_ERROR @ 1804155 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdcfcd0 [110111001111110011010000] vs 0x0 [0])
UVM_ERROR @ 1811155 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x109668 [100001001011001101000] vs 0x0 [0])