Simulation Results: sram_ctrl/main

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 96.26 %
  • code
  • 95.41 %
  • assert
  • 97.96 %
  • func
  • 95.40 %
  • block
  • 95.77 %
  • line
  • 96.46 %
  • branch
  • 93.53 %
  • toggle
  • 91.65 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 4.000s 712.782us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 38.232us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.016us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 192.363us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 37.143us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 367.613us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 12.016us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 37.143us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 223.000s 67415.773us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 54.000s 5298.842us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 16.000s 3742.101us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 135.000s 3522.541us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 115.000s 18553.072us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 35.000s 9482.267us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 59.000s 69016.798us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 25.000s 14473.573us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 385.894us 1 1 100.00
sram_ctrl_partial_access_b2b 278.000s 301690.781us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 1363.955us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 2642.711us 0 1 0.00
sram_ctrl_throughput_w_readback 5.000s 2819.711us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 17.000s 1084.675us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 3744.809us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 180.000s 73028.433us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 69.036us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 310.527us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 310.527us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 38.232us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.016us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 37.143us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 31.803us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 38.232us 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.016us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 37.143us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 31.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 7375.269us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 466.359us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 309.567us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 466.359us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 309.567us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 17.000s 1084.675us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 17.000s 1084.675us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 12.016us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 25.000s 14473.573us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 25.000s 14473.573us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 25.000s 14473.573us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 59.000s 69016.798us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 5.000s 3979.758us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 11.000s 7375.269us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 2081.078us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 712.782us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 4.000s 712.782us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 25.000s 14473.573us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 466.359us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 59.000s 69016.798us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 466.359us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 466.359us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 4.000s 712.782us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 466.359us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 43.000s 16089.606us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 7086493253483854205780524038964541812900251377025506355912369274073255142200 86
UVM_INFO @ 1363955036 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 48601230467805237053291516430443726109395955375931358696303013435682963714242 86
UVM_INFO @ 2642711208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 97787101920531626601213173349127245469966784486432622097732588308123375247971 86
UVM_INFO @ 2819710734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---