Simulation Results: sram_ctrl/ret

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.43 %
  • code
  • 82.37 %
  • assert
  • 97.53 %
  • func
  • 94.40 %
  • block
  • 93.83 %
  • line
  • 94.99 %
  • branch
  • 89.51 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 32.922us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 16.320us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.477us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 446.378us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 48.729us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 57.655us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 14.477us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 48.729us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 5.000s 370.884us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 4.000s 681.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 7.000s 1046.991us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 190.000s 4095.828us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 156.079us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 11.000s 460.540us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 3.000s 888.860us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 5.000s 951.374us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 61.024us 1 1 100.00
sram_ctrl_partial_access_b2b 157.000s 92659.665us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 77.560us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 315.993us 0 1 0.00
sram_ctrl_throughput_w_readback 1.000s 60.028us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 5771.795us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 30.674us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 6.000s 642.345us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 17.080us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 258.238us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 258.238us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.320us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.477us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 48.729us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 17.169us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 16.320us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.477us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 48.729us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 17.169us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 417.633us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 1407.216us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 120.583us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 1407.216us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 120.583us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 5771.795us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 5771.795us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.477us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 5.000s 951.374us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 5.000s 951.374us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 5.000s 951.374us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 3.000s 888.860us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 53.085us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 417.633us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 2.000s 201.434us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 32.922us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 32.922us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 5.000s 951.374us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 1407.216us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 3.000s 888.860us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 1407.216us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1407.216us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 32.922us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 1407.216us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 68.000s 4388.103us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 53363264890892280022525712136441361203355556315904336765755031063640209958624 86
UVM_INFO @ 77560447 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 88231332171488733299791075421468953323996625142755830396241341395699094852752 86
UVM_INFO @ 315993314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 110527850962856062692938645188780076286352996054336144350022952604654480993726 86
UVM_INFO @ 60027524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---