Simulation Results: sysrst_ctrl

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.64 %
  • code
  • 91.58 %
  • assert
  • 91.67 %
  • func
  • 61.67 %
  • line
  • 96.37 %
  • branch
  • 96.85 %
  • cond
  • 93.54 %
  • toggle
  • 100.00 %
  • FSM
  • 71.15 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.460s 2131.252us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 6.110s 2468.480us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.090s 2202.782us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 1.790s 2574.404us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 7.390s 6045.795us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 5.360s 2040.714us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 14.330s 10954.483us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.710s 2652.748us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.170s 2066.928us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 5.360s 2040.714us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.710s 2652.748us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 150.060s 95974.812us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 24.830s 26838.958us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.620s 3272.455us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 4.520s 2444.650us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 4.720s 2509.753us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.100s 2137.740us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.340s 3534.371us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 2.510s 2626.415us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.790s 10052.897us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 21.790s 33850.888us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 5.920s 17148.460us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 3.210s 2021.537us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.620s 2040.587us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 4.200s 2041.174us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 4.200s 2041.174us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.390s 6045.795us 1 1 100.00
sysrst_ctrl_csr_rw 5.360s 2040.714us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.710s 2652.748us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.590s 4881.325us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.390s 6045.795us 1 1 100.00
sysrst_ctrl_csr_rw 5.360s 2040.714us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.710s 2652.748us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 11.590s 4881.325us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 36.030s 22013.230us 1 1 100.00
sysrst_ctrl_tl_intg_err 68.350s 42485.544us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 68.350s 42485.544us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 9.140s 5397.297us 1 1 100.00