Simulation Results: uart

 
14/07/2026 15:30:29 DVSim: v1.49.12 sha: 84f5285 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.57 %
  • code
  • 92.52 %
  • assert
  • 98.56 %
  • func
  • 59.62 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.78 %
  • toggle
  • 74.67 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.220s 444.706us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.730s 15.200us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.620s 50.967us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.750s 312.872us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 1.020s 32.665us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.780s 119.613us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.620s 50.967us 1 1 100.00
uart_csr_aliasing 1.020s 32.665us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 42.540s 126976.657us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.220s 444.706us 1 1 100.00
uart_tx_rx 42.540s 126976.657us 1 1 100.00
parity_error 2 2 100.00
uart_intr 40.700s 33670.342us 1 1 100.00
uart_rx_parity_err 18.040s 38176.685us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 42.540s 126976.657us 1 1 100.00
uart_intr 40.700s 33670.342us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 37.700s 86298.187us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 33.270s 107498.866us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 30.920s 182129.203us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 40.700s 33670.342us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 40.700s 33670.342us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 40.700s 33670.342us 1 1 100.00
perf 1 1 100.00
uart_perf 161.910s 6025.580us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.180s 609.255us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.180s 609.255us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 75.550s 69877.191us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.080s 3005.112us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.250s 3558.692us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 23.200s 6696.730us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 442.050s 138973.924us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 49.720s 172744.329us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.630s 12.299us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.840s 12.513us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.650s 148.740us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.650s 148.740us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.730s 15.200us 1 1 100.00
uart_csr_rw 0.620s 50.967us 1 1 100.00
uart_csr_aliasing 1.020s 32.665us 1 1 100.00
uart_same_csr_outstanding 0.990s 30.853us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.730s 15.200us 1 1 100.00
uart_csr_rw 0.620s 50.967us 1 1 100.00
uart_csr_aliasing 1.020s 32.665us 1 1 100.00
uart_same_csr_outstanding 0.990s 30.853us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.870s 365.993us 1 1 100.00
uart_tl_intg_err 1.250s 377.829us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.250s 377.829us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 25.980s 5673.200us 1 1 100.00