Simulation Results

Simulation Results: adc_ctrl

15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
65.97 %

code
92.88 %

assert
91.90 %

func
13.12 %

line
98.22 %

branch
96.47 %

cond
86.39 %

toggle
99.53 %

FSM
83.78 %

Validation stages

V1		100.00%
V2		52.63%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	adc_ctrl_smoke	4.620s	5954.303us	1	1	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	0.940s	713.845us	1	1	100.00
csr_rw				1	1	100.00
	adc_ctrl_csr_rw	0.940s	612.743us	1	1	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	21.570s	26722.400us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	1.340s	750.682us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	1.280s	374.265us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	adc_ctrl_csr_rw	0.940s	612.743us	1	1	100.00
	adc_ctrl_csr_aliasing	1.340s	750.682us	1	1	100.00

10/19 passed

52.63 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	1	0.00
	adc_ctrl_filters_polled	0.690s	499.034us	0	1	0.00
filters_polled_fixed				0	1	0.00
	adc_ctrl_filters_polled_fixed	1.060s	484.713us	0	1	0.00
filters_interrupt				0	1	0.00
	adc_ctrl_filters_interrupt	1.180s	416.110us	0	1	0.00
filters_interrupt_fixed				0	1	0.00
	adc_ctrl_filters_interrupt_fixed	0.710s	383.780us	0	1	0.00
filters_wakeup				0	1	0.00
	adc_ctrl_filters_wakeup	0.740s	441.760us	0	1	0.00
filters_wakeup_fixed				0	1	0.00
	adc_ctrl_filters_wakeup_fixed	0.940s	280.287us	0	1	0.00
filters_both				0	1	0.00
	adc_ctrl_filters_both	0.900s	491.784us	0	1	0.00
clock_gating				0	1	0.00
	adc_ctrl_clock_gating	0.920s	275.239us	0	1	0.00
poweron_counter				1	1	100.00
	adc_ctrl_poweron_counter	6.930s	4949.773us	1	1	100.00
lowpower_counter				1	1	100.00
	adc_ctrl_lowpower_counter	3.710s	35108.135us	1	1	100.00
fsm_reset				1	1	100.00
	adc_ctrl_fsm_reset	49.540s	87596.284us	1	1	100.00
stress_all				0	1	0.00
	adc_ctrl_stress_all	0.920s	588.368us	0	1	0.00
alert_test				1	1	100.00
	adc_ctrl_alert_test	0.930s	450.442us	1	1	100.00
intr_test				1	1	100.00
	adc_ctrl_intr_test	1.110s	454.145us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	adc_ctrl_tl_errors	2.070s	624.982us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	adc_ctrl_tl_errors	2.070s	624.982us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	adc_ctrl_csr_hw_reset	0.940s	713.845us	1	1	100.00
	adc_ctrl_csr_rw	0.940s	612.743us	1	1	100.00
	adc_ctrl_csr_aliasing	1.340s	750.682us	1	1	100.00
	adc_ctrl_same_csr_outstanding	4.540s	2543.344us	1	1	100.00
tl_d_partial_access				4	4	100.00
	adc_ctrl_csr_hw_reset	0.940s	713.845us	1	1	100.00
	adc_ctrl_csr_rw	0.940s	612.743us	1	1	100.00
	adc_ctrl_csr_aliasing	1.340s	750.682us	1	1	100.00
	adc_ctrl_same_csr_outstanding	4.540s	2543.344us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	adc_ctrl_sec_cm	3.510s	8066.460us	1	1	100.00
	adc_ctrl_tl_intg_err	2.500s	8897.207us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	adc_ctrl_tl_intg_err	2.500s	8897.207us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	adc_ctrl_stress_all_with_rand_reset	3.850s	6394.374us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				9 test runs
	adc_ctrl_filters_polled	73655568749761016040325649554888723000147140070679922219553671455293637872118	386	UVM_INFO @ 499033821 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	26084028996907749850785477301058476524072216825460078225353928487524262453017	386	UVM_INFO @ 484713251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	71210374897604359546157103709753809612102069607720223907834867982747284775207	386	UVM_INFO @ 416110239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	115236690945700868012476067615357588540319688842470217732529740190011239356053	386	UVM_INFO @ 383780245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	92013944765951685116079312180803798364363987392417064921269619538366224063784	386	UVM_INFO @ 441759773 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	62366797652352654039409168866089637647475907268321129804844216411389799038808	386	UVM_INFO @ 280286839 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	29386550206120881861515626509476160657311092384430639909252178079694209269252	386	UVM_INFO @ 275238872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	24511683619186876409167840912629301258535804523079596564408343372287019619947	386	UVM_INFO @ 491784319 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	71668652418571669683752519783223916973083617563442093906109007105013705218969	387	UVM_INFO @ 588367554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---