Simulation Results: aes/masked

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.16 %
  • code
  • 94.11 %
  • assert
  • 98.23 %
  • func
  • 75.14 %
  • block
  • 94.23 %
  • line
  • 95.86 %
  • branch
  • 87.20 %
  • toggle
  • 97.82 %
  • FSM
  • 95.56 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 181.946us 1 1 100.00
smoke 1 1 100.00
aes_smoke 3.000s 157.844us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 83.272us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 113.329us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 6.000s 254.493us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 4.000s 215.300us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 71.699us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 113.329us 1 1 100.00
aes_csr_aliasing 4.000s 215.300us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 3.000s 157.844us 1 1 100.00
aes_config_error 3.000s 150.993us 1 1 100.00
aes_stress 4.000s 258.263us 1 1 100.00
key_length 3 3 100.00
aes_smoke 3.000s 157.844us 1 1 100.00
aes_config_error 3.000s 150.993us 1 1 100.00
aes_stress 4.000s 258.263us 1 1 100.00
back2back 2 2 100.00
aes_stress 4.000s 258.263us 1 1 100.00
aes_b2b 10.000s 384.484us 1 1 100.00
backpressure 1 1 100.00
aes_stress 4.000s 258.263us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 3.000s 157.844us 1 1 100.00
aes_config_error 3.000s 150.993us 1 1 100.00
aes_stress 4.000s 258.263us 1 1 100.00
aes_alert_reset 4.000s 1229.037us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 67.432us 1 1 100.00
aes_config_error 3.000s 150.993us 1 1 100.00
aes_alert_reset 4.000s 1229.037us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 104.927us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 10.000s 322.462us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 4.000s 1229.037us 1 1 100.00
stress 1 1 100.00
aes_stress 4.000s 258.263us 1 1 100.00
sideload 2 2 100.00
aes_stress 4.000s 258.263us 1 1 100.00
aes_sideload 2.000s 95.584us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 200.528us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 10802.200s 0.000us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 126.712us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 195.609us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 195.609us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 83.272us 1 1 100.00
aes_csr_rw 2.000s 113.329us 1 1 100.00
aes_csr_aliasing 4.000s 215.300us 1 1 100.00
aes_same_csr_outstanding 3.000s 103.735us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 83.272us 1 1 100.00
aes_csr_rw 2.000s 113.329us 1 1 100.00
aes_csr_aliasing 4.000s 215.300us 1 1 100.00
aes_same_csr_outstanding 3.000s 103.735us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 12.000s 1084.870us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 24.000s 2155.371us 0 1 0.00
aes_control_fi 9.000s 10038.784us 0 1 0.00
aes_cipher_fi 3.000s 74.223us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 75.601us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 75.601us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 75.601us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 75.601us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 299.132us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 510.732us 1 1 100.00
aes_tl_intg_err 2.000s 133.871us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 133.871us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 4.000s 1229.037us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 75.601us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 75.601us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 3.000s 157.844us 1 1 100.00
aes_stress 4.000s 258.263us 1 1 100.00
aes_alert_reset 4.000s 1229.037us 1 1 100.00
aes_core_fi 3.000s 80.048us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 150.993us 1 1 100.00
aes_stress 4.000s 258.263us 1 1 100.00
aes_core_fi 3.000s 80.048us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 75.601us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 70.690us 1 1 100.00
aes_stress 4.000s 258.263us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 4.000s 258.263us 1 1 100.00
aes_sideload 2.000s 95.584us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 70.690us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 70.690us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 70.690us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 70.690us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 70.690us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 4.000s 258.263us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 4.000s 258.263us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 24.000s 2155.371us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 24.000s 2155.371us 0 1 0.00
aes_control_fi 9.000s 10038.784us 0 1 0.00
aes_cipher_fi 3.000s 74.223us 1 1 100.00
aes_ctr_fi 2.000s 58.168us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 24.000s 2155.371us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 24.000s 2155.371us 0 1 0.00
aes_control_fi 9.000s 10038.784us 0 1 0.00
aes_cipher_fi 3.000s 74.223us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 74.223us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 24.000s 2155.371us 0 1 0.00
sec_cm_ctr_fsm_redun 1 3 33.33
aes_fi 24.000s 2155.371us 0 1 0.00
aes_control_fi 9.000s 10038.784us 0 1 0.00
aes_ctr_fi 2.000s 58.168us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 24.000s 2155.371us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 24.000s 2155.371us 0 1 0.00
aes_control_fi 9.000s 10038.784us 0 1 0.00
aes_cipher_fi 3.000s 74.223us 1 1 100.00
aes_ctr_fi 2.000s 58.168us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 4.000s 1229.037us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 24.000s 2155.371us 0 1 0.00
aes_control_fi 9.000s 10038.784us 0 1 0.00
aes_cipher_fi 3.000s 74.223us 1 1 100.00
aes_ctr_fi 2.000s 58.168us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 24.000s 2155.371us 0 1 0.00
aes_control_fi 9.000s 10038.784us 0 1 0.00
aes_cipher_fi 3.000s 74.223us 1 1 100.00
aes_ctr_fi 2.000s 58.168us 1 1 100.00
sec_cm_ctr_fsm_local_esc 1 3 33.33
aes_fi 24.000s 2155.371us 0 1 0.00
aes_control_fi 9.000s 10038.784us 0 1 0.00
aes_ctr_fi 2.000s 58.168us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 24.000s 2155.371us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 24.000s 2155.371us 0 1 0.00
aes_control_fi 9.000s 10038.784us 0 1 0.00
aes_cipher_fi 3.000s 74.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 10.000s 1538.399us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 105609517301826018333894974911752331898727281913088315680852647811561606867677 162969
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (aes_control_fi_vseq.sv:62) [aes_control_fi_vseq] wait timeout occurred! 1 test run
aes_control_fi 65064661000998113063186243445618524929163549268308866293898965583799044908411 148
UVM_INFO @ 10038783847 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
aes_stress_all 107226981154845698190880932356250474610555096171842865619613403883821021241268 None
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 107903369144766463407693585853691911357488739441635627665492133462268548966795 140
UVM_INFO @ 1538398782 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---