Simulation Results

Simulation Results: chip

15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
71.28 %

code
84.11 %

assert
97.37 %

func
32.37 %

line
94.32 %

branch
93.90 %

cond
88.70 %

toggle
86.47 %

FSM
57.14 %

Validation stages

V1		94.44%
V2		75.81%
V2S		100.00%
V3		57.69%
unmapped		63.64%

17/18 passed

94.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	135.310s	2343.295us	1	1	100.00
	chip_sw_example_rom	70.430s	2601.815us	1	1	100.00
	chip_sw_example_manufacturer	147.730s	3444.187us	1	1	100.00
	chip_sw_example_concurrency	156.570s	2319.789us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	195.890s	4867.429us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	220.100s	4188.244us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	2150.020s	30632.517us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	3785.980s	31550.247us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	chip_csr_mem_rw_with_rand_reset	55.600s	2496.809us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	3785.980s	31550.247us	1	1	100.00
	chip_csr_rw	220.100s	4188.244us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	6.890s	52.025us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	258.850s	4043.930us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	258.850s	4043.930us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	258.850s	4043.930us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	420.170s	4757.645us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	420.170s	4757.645us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	403.170s	4657.178us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	394.720s	4328.327us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	380.510s	4429.140us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1103.390s	8688.734us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1151.720s	9142.937us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	659.450s	8190.333us	1	1	100.00

210/277 passed

75.81 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	205.710s	5734.587us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	205.710s	5734.587us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	237.770s	3643.517us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	264.520s	6183.662us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	174.790s	4042.846us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	165.790s	3542.474us	1	1	100.00
	chip_tap_straps_testunlock0	457.790s	7714.523us	1	1	100.00
	chip_tap_straps_rma	106.020s	2984.880us	1	1	100.00
	chip_tap_straps_prod	828.840s	12692.465us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	479.330s	5368.196us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	479.330s	5368.196us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	658.140s	7953.131us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1757.550s	15381.571us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	351.090s	4094.313us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	528.600s	5695.171us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3994.320s	18601.998us	1	1	100.00
	chip_sw_aes_enc_jitter_en	162.670s	2955.698us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	749.910s	7358.680us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	146.030s	3131.951us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	699.440s	7588.374us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	161.670s	3469.303us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	472.150s	5233.301us	1	1	100.00
	chip_sw_clkmgr_jitter	142.990s	3038.761us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	215.040s	3120.599us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	470.610s	6262.099us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	282.390s	5505.106us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	146.350s	3140.813us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	282.390s	5505.106us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	203.030s	3048.373us	1	1	100.00
	chip_sw_aes_smoketest	148.970s	3531.825us	1	1	100.00
	chip_sw_aon_timer_smoketest	228.980s	3499.710us	1	1	100.00
	chip_sw_clkmgr_smoketest	127.370s	2603.911us	1	1	100.00
	chip_sw_csrng_smoketest	132.420s	2969.436us	1	1	100.00
	chip_sw_entropy_src_smoketest	1049.720s	7528.416us	1	1	100.00
	chip_sw_gpio_smoketest	163.670s	3081.106us	1	1	100.00
	chip_sw_hmac_smoketest	211.140s	2707.449us	1	1	100.00
	chip_sw_kmac_smoketest	152.800s	3316.416us	1	1	100.00
	chip_sw_otbn_smoketest	572.570s	5614.203us	1	1	100.00
	chip_sw_pwrmgr_smoketest	258.470s	5597.240us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	264.250s	5505.173us	1	1	100.00
	chip_sw_rv_plic_smoketest	126.650s	2291.576us	1	1	100.00
	chip_sw_rv_timer_smoketest	187.620s	3442.430us	1	1	100.00
	chip_sw_rstmgr_smoketest	161.740s	2561.024us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	179.850s	3523.652us	1	1	100.00
	chip_sw_uart_smoketest	154.440s	3159.652us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	125.660s	2663.651us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	297.370s	4469.033us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	7723.470s	59796.801us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3071.870s	15878.635us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	10.138s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	1091.940s	14397.689us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	873.860s	14603.518us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	6987.370s	52297.461us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7215.690s	55005.660us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	62.230s	2394.423us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	62.230s	2394.423us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	3785.980s	31550.247us	1	1	100.00
	chip_same_csr_outstanding	1032.690s	15026.680us	1	1	100.00
	chip_csr_hw_reset	195.890s	4867.429us	1	1	100.00
	chip_csr_rw	220.100s	4188.244us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	3785.980s	31550.247us	1	1	100.00
	chip_same_csr_outstanding	1032.690s	15026.680us	1	1	100.00
	chip_csr_hw_reset	195.890s	4867.429us	1	1	100.00
	chip_csr_rw	220.100s	4188.244us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	47.130s	1867.756us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	5.350s	53.200us	1	1	100.00
	xbar_smoke_large_delays	42.310s	7304.983us	1	1	100.00
	xbar_smoke_slow_rsp	43.360s	5147.385us	1	1	100.00
	xbar_random_zero_delays	37.560s	584.041us	1	1	100.00
	xbar_random_large_delays	336.510s	59324.735us	1	1	100.00
	xbar_random_slow_rsp	213.470s	24225.150us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	26.130s	860.349us	1	1	100.00
	xbar_error_and_unmapped_addr	33.360s	1353.730us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	52.400s	2212.405us	1	1	100.00
	xbar_error_and_unmapped_addr	33.360s	1353.730us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	5.440s	87.802us	1	1	100.00
	xbar_access_same_device_slow_rsp	476.080s	55943.032us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	44.630s	1841.239us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	6.690s	41.328us	1	1	100.00
	xbar_stress_all_with_error	156.960s	6491.829us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	117.340s	447.725us	1	1	100.00
	xbar_stress_all_with_reset_error	16.670s	74.323us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3071.870s	15878.635us	1	1	100.00
rom_e2e_shutdown_output				0	1	0.00
	rom_e2e_shutdown_output	446.330s	6890.246us	0	1	0.00
rom_e2e_shutdown_exception_c				0	1	0.00
	rom_e2e_shutdown_exception_c	484.240s	5185.252us	0	1	0.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	29.791s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	10.085s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	13.886s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	38.532s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	9.169s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	31.305s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	20.836s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	53.986s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	41.320s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	20.420s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	34.298s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	32.898s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	16.863s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	26.681s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	35.163s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	18.690s	10.360us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	18.590s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	18.910s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	20.180s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	21.040s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	22.890s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	18.730s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	25.670s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19.630s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	19.550s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	21.460s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.850s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	19.450s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	21.830s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	21.430s	10.300us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	34.973s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	75.067s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	87.835s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	66.651s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	85.749s	0.000us	0	1	0.00
rom_e2e_keymgr_init				3	3	100.00
	rom_e2e_keymgr_init_rom_ext_meas	5956.770s	28692.662us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	6039.970s	28009.054us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	6289.970s	27874.171us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3292.810s	15487.695us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2950.510s	35053.166us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2950.510s	35053.166us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	157.500s	2702.793us	1	1	100.00
	chip_sw_aes_enc_jitter_en	162.670s	2955.698us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	139.090s	3092.199us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	146.060s	3210.175us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1301.970s	11096.823us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	171.040s	2961.920us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	344.280s	5231.358us	1	1	100.00
chip_sw_all_escalation_resets				0	1	0.00
	chip_sw_all_escalation_resets	185.700s	2719.263us	0	1	0.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	457.730s	4700.626us	1	1	100.00
	chip_plic_all_irqs_10	241.030s	4007.726us	1	1	100.00
	chip_plic_all_irqs_20	382.450s	4904.928us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	243.810s	3204.150us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1026.800s	11109.976us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	237.980s	3522.342us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	156.100s	2760.386us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.138s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	868.560s	7571.204us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1234.510s	9576.166us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	852.100s	7788.233us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9095.210s	255187.638us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	243.190s	3638.960us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	258.470s	5597.240us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	243.190s	3638.960us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	471.830s	7778.731us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	471.830s	7778.731us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	371.150s	7152.112us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	377.530s	6140.116us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	647.750s	6138.835us	1	1	100.00
	chip_sw_aes_idle	146.060s	3210.175us	1	1	100.00
	chip_sw_hmac_enc_idle	186.080s	3624.842us	1	1	100.00
	chip_sw_kmac_idle	165.180s	2750.441us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	299.660s	4353.617us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	291.400s	4860.155us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	318.780s	4584.394us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	321.440s	4655.247us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	795.930s	11445.340us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	410.560s	3596.529us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	373.780s	4721.933us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	399.880s	4278.629us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	411.940s	5236.704us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	427.470s	4871.381us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	338.310s	4987.819us	1	1	100.00
	chip_sw_ast_clk_outputs	658.140s	7953.131us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	250.280s	5961.559us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	399.880s	4278.629us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	411.940s	5236.704us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	351.090s	4094.313us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	528.600s	5695.171us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3994.320s	18601.998us	1	1	100.00
	chip_sw_aes_enc_jitter_en	162.670s	2955.698us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	749.910s	7358.680us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	146.030s	3131.951us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	699.440s	7588.374us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	161.670s	3469.303us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	472.150s	5233.301us	1	1	100.00
	chip_sw_clkmgr_jitter	142.990s	3038.761us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	108.610s	2822.108us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	378.330s	4860.316us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	630.690s	7350.383us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4243.950s	24623.089us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	176.360s	3554.156us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	183.400s	3488.588us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	787.980s	8954.393us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	180.540s	3896.922us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	372.580s	6187.927us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1270.320s	19068.965us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	7145.200s	70188.965us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	658.140s	7953.131us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	414.870s	5116.471us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	273.030s	3431.747us	1	1	100.00
chip_sw_clkmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	185.700s	2719.263us	0	1	0.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	868.560s	7571.204us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1211.760s	8175.562us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				0	1	0.00
	chip_sw_csrng_fuse_en_sw_app_read_test	160.420s	3081.781us	0	1	0.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	474.420s	6944.565us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	160.530s	3322.101us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	5625.690s	28586.104us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	124.980s	2346.635us	1	1	100.00
	chip_sw_edn_entropy_reqs	881.510s	7707.625us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	124.980s	2346.635us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1211.760s	8175.562us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	159.830s	2991.426us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1009.230s	19785.350us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	509.960s	4725.576us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	528.600s	5695.171us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	331.170s	3484.075us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	351.090s	4094.313us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3384.220s	43423.026us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1009.230s	19785.350us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	210.150s	3646.970us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	949.770s	8907.171us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	199.070s	3112.847us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3384.220s	43423.026us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	199.070s	3112.847us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	199.070s	3112.847us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	199.070s	3112.847us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	199.070s	3112.847us	0	1	0.00
chip_sw_flash_lc_escalate_en				0	1	0.00
	chip_sw_all_escalation_resets	185.700s	2719.263us	0	1	0.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	257.320s	10150.765us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	531.650s	5732.674us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	414.330s	6272.230us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	414.330s	6272.230us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	165.470s	3253.450us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	146.030s	3131.951us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	186.080s	3624.842us	1	1	100.00
chip_sw_hmac_all_configurations				0	1	0.00
	chip_sw_hmac_oneshot	1676.250s	12018.587us	0	1	0.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1651.260s	12026.870us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	439.200s	5377.510us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	528.280s	5857.510us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	402.180s	5284.860us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	317.540s	4063.740us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	949.770s	8907.171us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	699.440s	7588.374us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1190.030s	8906.913us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1301.970s	11096.823us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	5844.630s	20018.442us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	200.610s	2904.670us	1	1	100.00
	chip_sw_kmac_mode_kmac	216.190s	3442.447us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	161.670s	3469.303us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	949.770s	8907.171us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	635.200s	10226.211us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	157.600s	2900.631us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	536.800s	5045.112us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	165.180s	2750.441us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	344.280s	5231.358us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	165.790s	3542.474us	1	1	100.00
	chip_tap_straps_rma	106.020s	2984.880us	1	1	100.00
	chip_tap_straps_prod	828.840s	12692.465us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	140.530s	3619.486us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	635.200s	10226.211us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	635.200s	10226.211us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	635.200s	10226.211us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1010.050s	9637.162us	1	1	100.00
chip_sw_lc_ctrl_broadcast				20	22	90.91
	chip_sw_flash_ctrl_lc_rw_en	199.070s	3112.847us	0	1	0.00
	chip_sw_flash_rma_unlocked	3384.220s	43423.026us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	229.690s	3468.949us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	622.710s	7834.195us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	591.020s	8265.940us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	542.810s	7766.037us	0	1	0.00
	chip_sw_lc_ctrl_transition	635.200s	10226.211us	1	1	100.00
	chip_sw_keymgr_key_derivation	949.770s	8907.171us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	338.140s	9705.934us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	611.910s	9339.418us	1	1	100.00
	chip_prim_tl_access	257.320s	10150.765us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	250.280s	5961.559us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	410.560s	3596.529us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	373.780s	4721.933us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	399.880s	4278.629us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	411.940s	5236.704us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	427.470s	4871.381us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	338.310s	4987.819us	1	1	100.00
	chip_tap_straps_dev	165.790s	3542.474us	1	1	100.00
	chip_tap_straps_rma	106.020s	2984.880us	1	1	100.00
	chip_tap_straps_prod	828.840s	12692.465us	1	1	100.00
	chip_rv_dm_lc_disabled	306.160s	7753.460us	1	1	100.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	182.280s	3497.435us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	113.250s	3735.988us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	109.790s	3524.647us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	158.310s	3780.494us	1	1	100.00
chip_lc_test_locked				2	2	100.00
	chip_sw_lc_walkthrough_testunlocks	1394.870s	23991.977us	1	1	100.00
	chip_rv_dm_lc_disabled	306.160s	7753.460us	1	1	100.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	602.340s	10116.186us	0	1	0.00
	chip_sw_lc_walkthrough_prod	610.380s	9517.186us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	602.560s	8366.241us	1	1	100.00
	chip_sw_lc_walkthrough_rma	407.510s	6076.241us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1394.870s	23991.977us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	88.960s	2588.085us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	68.700s	2937.159us	1	1	100.00
	rom_volatile_raw_unlock	73.077s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	4172.960s	17031.729us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3994.320s	18601.998us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	647.750s	6138.835us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	647.750s	6138.835us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	647.750s	6138.835us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	337.280s	4039.055us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	635.200s	10226.211us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1009.230s	19785.350us	1	1	100.00
	chip_sw_otbn_mem_scramble	337.280s	4039.055us	1	1	100.00
	chip_sw_keymgr_key_derivation	949.770s	8907.171us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	325.780s	4373.666us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	184.460s	3047.476us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1009.230s	19785.350us	1	1	100.00
	chip_sw_otbn_mem_scramble	337.280s	4039.055us	1	1	100.00
	chip_sw_keymgr_key_derivation	949.770s	8907.171us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	325.780s	4373.666us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	184.460s	3047.476us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	635.200s	10226.211us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	294.440s	4778.925us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	140.530s	3619.486us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	229.690s	3468.949us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	622.710s	7834.195us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	591.020s	8265.940us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	542.810s	7766.037us	0	1	0.00
	chip_sw_lc_ctrl_transition	635.200s	10226.211us	1	1	100.00
	chip_prim_tl_access	257.320s	10150.765us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	257.320s	10150.765us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	869.540s	8139.428us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	174.750s	5168.160us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	1012.660s	26314.968us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	285.110s	7869.359us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_por_reset	479.700s	8151.880us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	402.040s	6469.025us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	635.700s	20236.416us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				0	2	0.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	392.450s	9819.753us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	471.830s	7778.731us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	781.890s	12459.376us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	396.570s	5766.103us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	174.750s	5168.160us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	264.500s	4748.796us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	390.990s	8775.805us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	306.400s	7797.268us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	182.990s	3052.720us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	626.260s	13299.196us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	637.670s	7831.002us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1234.320s	13249.193us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	2114.800s	34980.662us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	168.510s	2473.041us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	185.700s	2719.263us	0	1	0.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	338.140s	9705.934us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	338.140s	9705.934us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	1234.320s	13249.193us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	626.260s	13299.196us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	396.570s	5766.103us	1	1	100.00
	chip_sw_pwrmgr_smoketest	258.470s	5597.240us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	218.090s	5403.118us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	494.870s	6911.935us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	315.970s	5121.901us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1026.800s	11109.976us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	141.180s	2781.907us	1	1	100.00
chip_sw_rstmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	185.700s	2719.263us	0	1	0.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1234.510s	9576.166us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	535.460s	5424.364us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	543.610s	5341.982us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	184.120s	2978.040us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	184.460s	3047.476us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	494.870s	6911.935us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	494.870s	6911.935us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	181.080s	2741.715us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	1352.410s	17864.640us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	972.740s	13450.744us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	218.090s	5403.118us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	244.540s	3329.920us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	1387.080s	13784.776us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	106.020s	2984.880us	1	1	100.00
chip_rv_dm_lc_disabled				1	1	100.00
	chip_rv_dm_lc_disabled	306.160s	7753.460us	1	1	100.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	457.730s	4700.626us	1	1	100.00
	chip_plic_all_irqs_10	241.030s	4007.726us	1	1	100.00
	chip_plic_all_irqs_20	382.450s	4904.928us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	208.410s	3256.988us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	171.540s	2900.005us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3071.870s	15878.635us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	524.730s	7406.619us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	171.000s	3766.808us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	200.050s	3096.607us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	158.210s	2971.402us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	325.780s	4373.666us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	472.150s	5233.301us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	329.690s	8176.147us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	435.260s	8000.864us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	611.910s	9339.418us	1	1	100.00
chip_sw_sram_lc_escalation				1	2	50.00
	chip_sw_all_escalation_resets	185.700s	2719.263us	0	1	0.00
	chip_sw_data_integrity_escalation	479.330s	5368.196us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	637.670s	7831.002us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1060.440s	23385.753us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	190.580s	2639.221us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	191.590s	3616.718us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	281.550s	4050.622us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1060.440s	23385.753us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1060.440s	23385.753us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2609.970s	20831.384us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2609.970s	20831.384us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	365.700s	6201.633us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2950.510s	35053.166us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	153.620s	2392.677us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	154.660s	2746.943us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	257.410s	3275.338us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	365.550s	4045.607us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	1057.450s	8579.986us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5779.590s	31491.300us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1819.770s	12878.665us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	157.480s	2730.094us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	160.690s	3207.429us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	148.190s	2478.541us	1	1	100.00

15/26 passed

57.69 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	10065.230s	68553.660us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1148.580s	6576.472us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	200.590s	4088.870us	0	1	0.00
	rom_e2e_jtag_debug_dev	199.670s	4738.608us	0	1	0.00
	rom_e2e_jtag_debug_rma	230.810s	4154.043us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	68.810s	2751.150us	0	1	0.00
	rom_e2e_jtag_inject_dev	78.660s	3747.509us	0	1	0.00
	rom_e2e_jtag_inject_rma	253.220s	4075.801us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	21.061s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	276.410s	3418.793us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	307.740s	2896.916us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	621.380s	4686.613us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	734.960s	6918.717us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	252.560s	2382.809us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	625.450s	5424.488us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	70.270s	2329.811us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	188.590s	3240.777us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				0	1	0.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	366.760s	5569.622us	0	1	0.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	367.460s	5368.893us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1234.320s	13249.193us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	200.590s	4088.870us	0	1	0.00
	rom_e2e_jtag_debug_dev	199.670s	4738.608us	0	1	0.00
	rom_e2e_jtag_debug_rma	230.810s	4154.043us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	365.850s	5238.298us	1	1	100.00
chip_sw_plic_alerts				0	1	0.00
	chip_sw_all_escalation_resets	185.700s	2719.263us	0	1	0.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5660.540s	38026.233us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5660.540s	38026.233us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	197.710s	2943.555us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	420.170s	4757.645us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3228.570s	18359.033us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	208.070s	3009.275us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	18.830s	10.320us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	5.040s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	166.480s	2896.064us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	225.830s	3332.864us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	264.150s	4067.306us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	8.140s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	190.330s	3167.882us	1	1	100.00
	ate_bootstrap_flash_erase	662.790s	10010.320us	0	1	0.00
	ate_bootstrap_one_frame	6364.140s	43170.945us	1	1	100.00
	ate_bootstrap_disjoint	9680.440s	79228.078us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	8348501850682142670837853105278798787949788374387616978927046159468012314990	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	103812331511821454681570422817663545723590681450887931925353947153456225554629	None	Another command (pid=424982) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=447076) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=424219) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	106090577207734604743414125159577123342176473522110502118809464184986178368315	None	Another command (pid=608154) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=560009) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=565076) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	106102367736437538544514851400933385204630889864027842644163563854807361338217	None	Another command (pid=640045) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=590383) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=630126) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	15985854660141175940117539902793947736178121502481077836861058488254140030080	None	Another command (pid=674980) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=673583) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=697626) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	46991000033680029106827476684888889412752566128965113986578310870524254803930	None	Another command (pid=464962) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=648293) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=649430) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	72278019260097078726426721550224711883398629349743667294668930401506414450953	None	Another command (pid=375626) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=424982) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=447076) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	47085649753583044288594977191190312608830893296912664606363355444048642585139	None	Another command (pid=594792) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=579823) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=613740) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	102395232555643176427021147949485506053545576646185764422712123948352300558873	None	Another command (pid=693705) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=696336) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=668593) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	64644777351503022023519657896101951242643986460144215927483485036970748219660	None	Another command (pid=616534) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=673924) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=670019) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	10405650353489093463980763767551550531940788456125225622591223437758171681683	None	Another command (pid=649777) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=643569) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=650694) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	37488438167303864856612791399821520454713853172965890112160650252032299889401	None	---- STDERR ---- Another command (pid=447076) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	108121272128023532992520430798080662552550312878066164004970669770517775170757	None	Another command (pid=419379) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=561618) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=468960) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	113445116168920275778366013555566533684381008087530200928558349019840510544305	None	---- STDERR ---- Another command (pid=577045) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=566091) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	107775133018676849693282584727503944957299092298939407322772567113591067846985	None	Another command (pid=601438) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=595111) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=594792) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	49174352805707578769376836000667992868033183817078006989700106271283743579575	None	Another command (pid=628930) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=648293) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=649430) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	68081870901532763697649197457829436316945488105763331972834881139825740717987	None	Another command (pid=375626) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=424982) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=447076) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	36997249904035836531813817660809396595852242426138030075234893637070553212485	None	Another command (pid=564647) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=460477) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=536177) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	24172707243630522789028881705713587316517413945610857070954433961195932255109	None	Another command (pid=601438) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=595111) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=597573) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	72792082493569054077932650593597228339714401001767580061800778246580570434612	None	Another command (pid=460477) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=536177) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=419379) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	65384755039164646597280858126852169760306298326568266873583051359845350911668	None	Another command (pid=614805) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=608154) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=560009) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	72535700967575903613849805677140001747867219505321145103187690730471915122520	None	Another command (pid=478064) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=556717) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=479108) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	106370925487553978795537862271826124898932448488285165037491499805056636775217	None	---- STDERR ---- Another command (pid=424982) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=447076) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	46749929141955929037855811541002886900129633339677425639684407428662718256044	None	Another command (pid=424982) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=447076) is running. Waiting for it to complete on the server (server_pid=278324)... Another command (pid=457397) is running. Waiting for it to complete on the server (server_pid=278324)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				7 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	104157232450348919784436114875774414268460355304318450475511856498563346008701	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	14929478012800744601631383348027310850804679866676141069960298698768930556713	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	97956974899467466659405528889734991459744837326441701999299743504545295355089	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	60174469031710101829033509707319974683683548181767504307348959904883807712798	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	83864485089890963919087600695764257744563715404527990908275431006306884539873	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	113773765369074018718840115869299415719940849073837399727465535658794655814838	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	99947981503337086819891000708704147688985455784753073469235078454993314961713	310	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	45131006482014398410957176535245922197625254053642993533845361071248206627475	366	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	56526200020354237979888495662039582436002573747127409548096190378092286314518	365	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	18419042326672257246937517563384351350237048047674561348484168284835761440720	368	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	80069950729603129785160522022158851845140639099061245908082201393177887626785	328	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	152175347458007458082197632434705024502398440598359556071562074801441871599	328	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	113334855783573537728100012206727555546465818381517151814076338142573124463108	327	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				4 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	85515731420707219390296731621986237939410287057596408407487804198544516027539	344	UVM_ERROR @ 13299.196000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 13299.196000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	39507973316455826319037751373708306903158728986336843855610487107855158174897	327	UVM_ERROR @ 9819.752500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 9819.752500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	6968928328250678537018401233905755333659441785483969052303656698636511896222	328	UVM_ERROR @ 8775.804500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 8775.804500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	31780266608182400012033780438096344017374386612560522663837927170735593904948	319	UVM_ERROR @ 7778.731000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7778.731000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				3 test runs
	chip_sw_all_escalation_resets	115770778524773518469143230888289328143390936171793189029178048660796850429048	317	UVM_ERROR @ 2719.262586 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 2719.262586 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_otp_ctrl_escalation	62376990499000017052360937334170180763677940539094533045843414752059533303759	316	UVM_ERROR @ 3240.777232 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3240.777232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_csrng_fuse_en_sw_app_read_test	24796735260876031217879840293786481193409253744234398305249070459152946822157	312	UVM_ERROR @ 3081.780828 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3081.780828 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	9180728169606792613958734409761260900695181242113476386695106848241971312023	369	UVM_INFO @ 10116.186200 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	25392810910624645754990841197878874625853743285832733559749883468408946938153	369	UVM_INFO @ 9517.185900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	20925647742125236772428331354471438598994927645319274794108128052619247445251	341	UVM_INFO @ 6076.240680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				3 test runs
	chip_sw_hmac_oneshot	3557156217352570077089735486240909529207294664954967171767984537791390498383	336	UVM_INFO @ 12018.587299 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_hmac_multistream	78193965712583726320613225585924979038905743175984352314129677826784028820245	346	UVM_INFO @ 12026.870081 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	18388837016303433620023268879440581838387014873055087976080394449154655487749	338	UVM_INFO @ 20018.441715 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	43706708339440569641518741328600008895077929106920109512234781847979006586399	325	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	81445430696502605854897738204767143779744656253016777652486958466152009916268	326	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	79723453012872110038994444194740002563622857373702746037603728940826741106673	328	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				2 test runs
	chip_tl_errors	26432239330808434730663630198046737163674216384221027397208607311264843007226	217	TL item was: req: (cip_tl_seq_item@32608) { a_addr: 'h1056c a_data: 'h19d68d46 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h1ba9d d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2394.422826 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_csr_mem_rw_with_rand_reset	73947031568210647010151121326228599565471410983217179794427707112058833444801	224	TL item was: req: (cip_tl_seq_item@30942) { a_addr: 'h106a0 a_data: 'h40e5eae7 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h1b6fd d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2496.809424 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	13680008115466433342578616972141407664582005580140464464986691018064976487028	362	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	46240918879511531771257162841006849746704716640013143731653036692069448347595	325	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	115112332392237069803341438099469501073307390889655962489534874350389121211362	365	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	104874938321221201358962577660029365282666310347025949622087855250151456352772	326	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	84666236615937338329150047733273392431166935933186892370049891131365169278158	301	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	110820021036966170516404799870746504106008178556784180793637380874632401654950	327	UVM_INFO @ 3766.808372 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	67496885680920353239999028365363441784908358358943527695461139103510029377104	309	UVM_INFO @ 3112.847212 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	103228173025701540372457869727363584192899189697094571291489251502406492623183	342	UVM_INFO @ 7766.036925 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	40393547194486102935942403027956886884207457961739035603043849276023997104616	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	93195709229320891319369995182798199871259809465895672034294689145491001348815	320	UVM_ERROR @ 5168.160103 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 5168.160103 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	8463661886313053682836886223060852461318300195260145838443854700075775122806	313	UVM_ERROR @ 3052.719554 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3052.719554 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	32642161573527970003370317782728993269045873905876267099387813390422752147197	332	UVM_INFO @ 35053.166046 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:297)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	42096574192873097053449589952751760156804939705087822947460984907740760784745	307	UVM_INFO @ 2961.919867 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	40579682265744138742425770944812712796961050771672257476076520290958159931753	308	UVM_INFO @ 2760.386305 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	84697679367611620410519450679876012930046861422302007303197477208271105981735	None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	101112156022721010917574248194186679094694892155522191548007082656041580826413	343	UVM_INFO @ 3418.792861 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: *				1 test run
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	81953919137207582081591059766395834511196830249216624938024314722288765142176	316	UVM_INFO @ 5569.622000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.				1 test run
	chip_sw_rv_dm_access_after_wakeup	21878928301681636306378917955307392186654748421771716573658331880365640009249	329	UVM_INFO @ 13784.776328 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_idle_load	113997067623746167175911233293695981241468440122086397309832860076709978986530	318	UVM_INFO @ 14397.688990 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_sleep_load	48869093962550007015948325410227438926182284800375969663032679171196546809469	329	UVM_INFO @ 14603.517530 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	60176425066248289017068616271141035947860024084095103096040455303113564423610	327	UVM_INFO @ 15381.571103 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	15474723013670082891347605018184363924125479903762722958948253604865989545746	272	UVM_INFO @ 10010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:--*				1 test run
	rom_e2e_shutdown_exception_c	110044611443665855925086006808669268498980233665594405358968483515235089114969	319	" == "OpenTitan:4001-0002-01 " UVM_INFO @ 5185.251561 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:--*				1 test run
	rom_e2e_shutdown_output	96627406889088472140300414012124086667483753079792765347035556177238437389827	312	" == "OpenTitan:4001-0002-01 " UVM_INFO @ 6890.246307 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	4163118979370946458886954084090690839848530845537887263884607510728818365706	326	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	23938788432758993735286875150527924902299632653372597009601451036376382106267	326	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	73770880014104715082110809886226875446995178682417160197370900219115100016427	327	UVM_ERROR @ 4469.033208 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4469.033208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---