Simulation Results: clkmgr

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.30 %
  • code
  • 96.83 %
  • assert
  • 92.94 %
  • func
  • 81.13 %
  • line
  • 98.52 %
  • branch
  • 97.80 %
  • cond
  • 89.13 %
  • toggle
  • 98.71 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
66.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.020s 152.853us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.730s 28.640us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.800s 16.878us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 9.070s 2175.626us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.020s 60.521us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.200s 49.679us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.800s 16.878us 1 1 100.00
clkmgr_csr_aliasing 1.020s 60.521us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.760s 17.050us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.380s 130.100us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.720s 18.852us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.660s 16.144us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.020s 152.853us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.830s 324.165us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.710s 1293.515us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.830s 324.165us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 6.440s 1538.265us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.690s 15.339us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.440s 169.169us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.440s 169.169us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.730s 28.640us 1 1 100.00
clkmgr_csr_rw 0.800s 16.878us 1 1 100.00
clkmgr_csr_aliasing 1.020s 60.521us 1 1 100.00
clkmgr_same_csr_outstanding 0.970s 95.229us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.730s 28.640us 1 1 100.00
clkmgr_csr_rw 0.800s 16.878us 1 1 100.00
clkmgr_csr_aliasing 1.020s 60.521us 1 1 100.00
clkmgr_same_csr_outstanding 0.970s 95.229us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 0.770s 31.810us 0 1 0.00
clkmgr_tl_intg_err 36.200s 10081.805us 0 1 0.00
shadow_reg_update_error 0 1 0.00
clkmgr_shadow_reg_errors 456.740s 200000.000us 0 1 0.00
shadow_reg_read_clear_staged_value 0 1 0.00
clkmgr_shadow_reg_errors 456.740s 200000.000us 0 1 0.00
shadow_reg_storage_error 0 1 0.00
clkmgr_shadow_reg_errors 456.740s 200000.000us 0 1 0.00
shadowed_reset_glitch 0 1 0.00
clkmgr_shadow_reg_errors 456.740s 200000.000us 0 1 0.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 0.780s 23.369us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 36.200s 10081.805us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.830s 324.165us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.710s 1293.515us 1 1 100.00
sec_cm_meas_config_shadow 0 1 0.00
clkmgr_shadow_reg_errors 456.740s 200000.000us 0 1 0.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.920s 125.862us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.840s 79.485us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.080s 28.472us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.750s 17.466us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.860s 21.142us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.800s 16.878us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.770s 31.810us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.800s 16.878us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.800s 16.878us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.770s 31.810us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.290s 476.833us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 33.760s 5399.445us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
clkmgr_shadow_reg_errors 1568617618689139776067555974772661684749733290019909323679701267542222817543 76
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger! 1 test run
clkmgr_shadow_reg_errors_with_csr_rw 79879216515788399999401126249745726631519832135270883767950523356311242310267 75
UVM_INFO @ 23369434 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 39643660678316034665340278797063040313971029151540388170707194892870026921910 86
UVM_INFO @ 31810181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 1 test run
clkmgr_tl_intg_err 17889337526465224230557029376307575903206767284803858353139514411996127393885 166
UVM_INFO @ 10081804768 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---