Simulation Results: csrng

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.11 %
  • code
  • 92.38 %
  • assert
  • 94.54 %
  • func
  • 71.40 %
  • block
  • 97.05 %
  • line
  • 97.76 %
  • branch
  • 92.68 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 2.000s 18.804us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 178.469us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 26.479us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 5.000s 158.738us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 3.000s 129.982us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 24.162us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 26.479us 1 1 100.00
csrng_csr_aliasing 3.000s 129.982us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 140.771us 1 1 100.00
alerts 1 1 100.00
csrng_alert 11.000s 1035.414us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 27.803us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 3.000s 104.172us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 3.000s 104.172us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 95.000s 8953.095us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 37.863us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 135.480us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 225.141us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 225.141us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 3.000s 178.469us 1 1 100.00
csrng_csr_rw 2.000s 26.479us 1 1 100.00
csrng_csr_aliasing 3.000s 129.982us 1 1 100.00
csrng_same_csr_outstanding 2.000s 52.868us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 3.000s 178.469us 1 1 100.00
csrng_csr_rw 2.000s 26.479us 1 1 100.00
csrng_csr_aliasing 3.000s 129.982us 1 1 100.00
csrng_same_csr_outstanding 2.000s 52.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 132.630us 1 1 100.00
csrng_tl_intg_err 3.000s 175.086us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 5.671us 0 1 0.00
csrng_csr_rw 2.000s 26.479us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 11.000s 1035.414us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 95.000s 8953.095us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 140.771us 1 1 100.00
csrng_err 2.000s 27.803us 1 1 100.00
csrng_sec_cm 3.000s 132.630us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 140.771us 1 1 100.00
csrng_err 2.000s 27.803us 1 1 100.00
csrng_sec_cm 3.000s 132.630us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 140.771us 1 1 100.00
csrng_err 2.000s 27.803us 1 1 100.00
csrng_sec_cm 3.000s 132.630us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 140.771us 1 1 100.00
csrng_err 2.000s 27.803us 1 1 100.00
csrng_sec_cm 3.000s 132.630us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 140.771us 1 1 100.00
csrng_err 2.000s 27.803us 1 1 100.00
csrng_sec_cm 3.000s 132.630us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 11.000s 1035.414us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 140.771us 1 1 100.00
csrng_err 2.000s 27.803us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 95.000s 8953.095us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 11.000s 1035.414us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 175.086us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 140.771us 1 1 100.00
csrng_err 2.000s 27.803us 1 1 100.00
csrng_sec_cm 3.000s 132.630us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 140.771us 1 1 100.00
csrng_err 2.000s 27.803us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 140.771us 1 1 100.00
csrng_err 2.000s 27.803us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 140.771us 1 1 100.00
csrng_err 2.000s 27.803us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 140.771us 1 1 100.00
csrng_err 2.000s 27.803us 1 1 100.00
csrng_sec_cm 3.000s 132.630us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 140.771us 1 1 100.00
csrng_err 2.000s 27.803us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3602.119s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 44093025567333755968955431054334404977795954544016361923937126607324296577986 100
UVM_INFO @ 104171985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (csrng_regwen_vseq.sv:67) virtual_sequencer [csrng_regwen_vseq] Was unable to flip INT_STATE_READ_ENABLE 1 test run
csrng_regwen 10803036697445039962894306846908212181477835876803921529810587259938623325597 99
UVM_INFO @ 5671273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 83336130985569834118848899268661798052739068101961838199147216992651489279558 None