Simulation Results: edn/edn0

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.63 %
  • code
  • 78.84 %
  • assert
  • 96.31 %
  • func
  • 81.75 %
  • line
  • 96.96 %
  • branch
  • 89.54 %
  • cond
  • 84.39 %
  • toggle
  • 75.98 %
  • FSM
  • 47.31 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.800s 25.585us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.850s 49.086us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.950s 29.573us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.730s 311.960us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.160s 195.703us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.060s 29.936us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.950s 29.573us 1 1 100.00
edn_csr_aliasing 1.160s 195.703us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.930s 83.474us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.930s 83.474us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.930s 83.474us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.020s 21.681us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.030s 76.222us 1 1 100.00
errs 1 1 100.00
edn_err 0.810s 21.752us 1 1 100.00
disable 2 2 100.00
edn_disable 0.850s 10.969us 1 1 100.00
edn_disable_auto_req_mode 1.040s 76.578us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.370s 117.619us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.850s 48.128us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.820s 15.815us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.440s 31.013us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.440s 31.013us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.850s 49.086us 1 1 100.00
edn_csr_rw 0.950s 29.573us 1 1 100.00
edn_csr_aliasing 1.160s 195.703us 1 1 100.00
edn_same_csr_outstanding 1.190s 53.152us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.850s 49.086us 1 1 100.00
edn_csr_rw 0.950s 29.573us 1 1 100.00
edn_csr_aliasing 1.160s 195.703us 1 1 100.00
edn_same_csr_outstanding 1.190s 53.152us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.950s 1171.841us 1 1 100.00
edn_tl_intg_err 1.640s 78.883us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 18.356us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.030s 76.222us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.950s 1171.841us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.950s 1171.841us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.950s 1171.841us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.950s 1171.841us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.030s 76.222us 1 1 100.00
edn_sec_cm 5.950s 1171.841us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.030s 76.222us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.640s 78.883us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 33.900s 1962.423us 1 1 100.00