Simulation Results: edn/edn1

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.96 %
  • code
  • 83.04 %
  • assert
  • 98.44 %
  • func
  • 79.41 %
  • line
  • 98.03 %
  • branch
  • 92.86 %
  • cond
  • 87.38 %
  • toggle
  • 91.46 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.830s 19.258us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 64.383us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.810s 14.092us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.690s 575.495us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.040s 70.817us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.400s 26.828us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.810s 14.092us 1 1 100.00
edn_csr_aliasing 1.040s 70.817us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.070s 44.211us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.070s 44.211us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.070s 44.211us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.860s 37.975us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.950s 25.027us 1 1 100.00
errs 1 1 100.00
edn_err 0.860s 20.061us 1 1 100.00
disable 2 2 100.00
edn_disable 0.750s 72.325us 1 1 100.00
edn_disable_auto_req_mode 1.070s 162.713us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.050s 865.756us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.920s 44.438us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.860s 32.074us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.350s 88.322us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.350s 88.322us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 64.383us 1 1 100.00
edn_csr_rw 0.810s 14.092us 1 1 100.00
edn_csr_aliasing 1.040s 70.817us 1 1 100.00
edn_same_csr_outstanding 0.930s 24.889us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 64.383us 1 1 100.00
edn_csr_rw 0.810s 14.092us 1 1 100.00
edn_csr_aliasing 1.040s 70.817us 1 1 100.00
edn_same_csr_outstanding 0.930s 24.889us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.260s 876.913us 1 1 100.00
edn_tl_intg_err 1.320s 118.684us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.980s 86.225us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.950s 25.027us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.260s 876.913us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.260s 876.913us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.260s 876.913us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.260s 876.913us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.950s 25.027us 1 1 100.00
edn_sec_cm 2.260s 876.913us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.950s 25.027us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.320s 118.684us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 6.290s 3050.976us 1 1 100.00