Simulation Results: hmac

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.74 %
  • code
  • 97.17 %
  • assert
  • 97.60 %
  • func
  • 41.44 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.96 %
  • toggle
  • 100.00 %
  • FSM
  • 91.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.690s 254.270us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.780s 31.169us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.910s 14.839us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 13.010s 8156.101us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.630s 396.911us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 0.900s 35.728us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.910s 14.839us 1 1 100.00
hmac_csr_aliasing 2.630s 396.911us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 46.790s 5755.362us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 6.690s 446.164us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 195.800s 8794.976us 1 1 100.00
hmac_test_sha384_vectors 413.830s 24595.181us 1 1 100.00
hmac_test_sha512_vectors 352.370s 61266.174us 1 1 100.00
hmac_test_hmac256_vectors 8.090s 690.230us 1 1 100.00
hmac_test_hmac384_vectors 6.250s 904.718us 1 1 100.00
hmac_test_hmac512_vectors 9.050s 358.075us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 6.590s 208.035us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 141.750s 8437.179us 1 1 100.00
error 1 1 100.00
hmac_error 112.490s 64457.990us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 90.900s 12599.102us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.690s 254.270us 1 1 100.00
hmac_long_msg 46.790s 5755.362us 1 1 100.00
hmac_back_pressure 6.690s 446.164us 1 1 100.00
hmac_datapath_stress 141.750s 8437.179us 1 1 100.00
hmac_burst_wr 6.590s 208.035us 1 1 100.00
hmac_stress_all 72.980s 8144.048us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.690s 254.270us 1 1 100.00
hmac_long_msg 46.790s 5755.362us 1 1 100.00
hmac_back_pressure 6.690s 446.164us 1 1 100.00
hmac_datapath_stress 141.750s 8437.179us 1 1 100.00
hmac_wipe_secret 90.900s 12599.102us 1 1 100.00
hmac_test_sha256_vectors 195.800s 8794.976us 1 1 100.00
hmac_test_sha384_vectors 413.830s 24595.181us 1 1 100.00
hmac_test_sha512_vectors 352.370s 61266.174us 1 1 100.00
hmac_test_hmac256_vectors 8.090s 690.230us 1 1 100.00
hmac_test_hmac384_vectors 6.250s 904.718us 1 1 100.00
hmac_test_hmac512_vectors 9.050s 358.075us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.690s 254.270us 1 1 100.00
hmac_long_msg 46.790s 5755.362us 1 1 100.00
hmac_back_pressure 6.690s 446.164us 1 1 100.00
hmac_datapath_stress 141.750s 8437.179us 1 1 100.00
hmac_burst_wr 6.590s 208.035us 1 1 100.00
hmac_error 112.490s 64457.990us 1 1 100.00
hmac_wipe_secret 90.900s 12599.102us 1 1 100.00
hmac_test_sha256_vectors 195.800s 8794.976us 1 1 100.00
hmac_test_sha384_vectors 413.830s 24595.181us 1 1 100.00
hmac_test_sha512_vectors 352.370s 61266.174us 1 1 100.00
hmac_test_hmac256_vectors 8.090s 690.230us 1 1 100.00
hmac_test_hmac384_vectors 6.250s 904.718us 1 1 100.00
hmac_test_hmac512_vectors 9.050s 358.075us 1 1 100.00
hmac_stress_all 72.980s 8144.048us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 72.980s 8144.048us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.630s 34.856us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.660s 155.430us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.070s 642.527us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.070s 642.527us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.780s 31.169us 1 1 100.00
hmac_csr_rw 0.910s 14.839us 1 1 100.00
hmac_csr_aliasing 2.630s 396.911us 1 1 100.00
hmac_same_csr_outstanding 1.110s 184.728us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.780s 31.169us 1 1 100.00
hmac_csr_rw 0.910s 14.839us 1 1 100.00
hmac_csr_aliasing 2.630s 396.911us 1 1 100.00
hmac_same_csr_outstanding 1.110s 184.728us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.000s 363.270us 1 1 100.00
hmac_tl_intg_err 2.610s 186.255us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.610s 186.255us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.690s 254.270us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.580s 745.125us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 83.610s 13204.191us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.280s 886.527us 1 1 100.00