Simulation Results

Simulation Results: i2c

15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
87.88 %

code
82.14 %

assert
97.25 %

func
84.25 %

line
96.63 %

branch
92.90 %

cond
87.67 %

toggle
89.47 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	16.860s	2385.151us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	4.170s	3230.357us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	1.030s	77.446us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.900s	42.382us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.920s	1986.041us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.620s	60.270us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.190s	110.516us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.900s	42.382us	1	1	100.00
	i2c_csr_aliasing	1.620s	60.270us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.770s	6.904us	0	1	0.00
host_stress_all				1	1	100.00
	i2c_host_stress_all	954.380s	74986.200us	1	1	100.00
host_maxperf				1	1	100.00
	i2c_host_perf	16.860s	13285.674us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.990s	161.742us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	29.890s	12733.037us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	73.620s	2147.957us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.390s	568.293us	1	1	100.00
	i2c_host_fifo_fmt_empty	2.730s	304.419us	1	1	100.00
	i2c_host_fifo_reset_rx	2.910s	159.221us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	82.950s	12913.049us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	7.780s	2195.687us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.810s	15.790us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.020s	606.175us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	30.240s	51703.450us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	2.460s	1010.319us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	12.180s	6855.958us	1	1	100.00
	i2c_target_intr_smoke	4.990s	2334.848us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.910s	260.326us	1	1	100.00
	i2c_target_fifo_reset_tx	1.280s	236.857us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	8.230s	24153.409us	1	1	100.00
	i2c_target_stress_rd	12.180s	6855.958us	1	1	100.00
	i2c_target_intr_stress_wr	13.010s	10789.738us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.310s	6142.177us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	5.650s	762.590us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.780s	4693.393us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	17.070s	10012.110us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.610s	6536.532us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.380s	715.772us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	16.860s	13285.674us	1	1	100.00
	i2c_host_perf_precise	1.790s	251.227us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	7.780s	2195.687us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	5.950s	489.430us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.820s	927.834us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.080s	1236.138us	1	1	100.00
	i2c_target_nack_txstretch	1.730s	137.558us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	4.090s	381.472us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.550s	520.716us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.840s	19.092us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	1.010s	86.238us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	2.140s	491.940us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	2.140s	491.940us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	1.030s	77.446us	1	1	100.00
	i2c_csr_rw	0.900s	42.382us	1	1	100.00
	i2c_csr_aliasing	1.620s	60.270us	1	1	100.00
	i2c_same_csr_outstanding	1.170s	235.161us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	1.030s	77.446us	1	1	100.00
	i2c_csr_rw	0.900s	42.382us	1	1	100.00
	i2c_csr_aliasing	1.620s	60.270us	1	1	100.00
	i2c_same_csr_outstanding	1.170s	235.161us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.340s	285.942us	1	1	100.00
	i2c_sec_cm	1.030s	61.798us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.340s	285.942us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	2.750s	805.499us	1
target_error_intr				1
	i2c_target_unexp_stop	1.340s	46.320us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	13.630s	4696.539us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	36279713865839110809795321428342141881003237686249602844008685667341444571955	80	UVM_INFO @ 6903729 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	48455614993281502277618689591547273844511154022387896962634757160626441159370	81	UVM_INFO @ 15789645 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				2 test runs
	i2c_host_stress_all_with_rand_reset	99236949920505968705867244728407269424590957040203644803688260937482562614461	86	UVM_INFO @ 805499459 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	12767055936199813978493069569986212561375424810230951968286070576953622628443	108	UVM_INFO @ 4696538526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	110547156051560508109027924978236523468276876511407281315808973107376333395299	84	UVM_INFO @ 606174570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])				1 test run
	i2c_target_unexp_stop	48957775386434717781837418473015524947512022591847958620736703312668878505606	78	UVM_INFO @ 46319551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!				1 test run
	i2c_target_hrst	114592214549407878754937539941478601028276863267498241098605060219809947401950	79	UVM_INFO @ 10012109919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---