Simulation Results: keymgr

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.14 %
  • code
  • 93.48 %
  • assert
  • 97.72 %
  • func
  • 55.23 %
  • line
  • 98.72 %
  • branch
  • 97.53 %
  • cond
  • 93.44 %
  • toggle
  • 91.67 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 4.010s 225.629us 1 1 100.00
random 1 1 100.00
keymgr_random 3.090s 132.793us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.410s 62.610us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.950s 48.657us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 24.610s 5566.948us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 2.900s 831.145us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.120s 41.962us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.950s 48.657us 1 1 100.00
keymgr_csr_aliasing 2.900s 831.145us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 8.100s 1122.686us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 5.880s 1368.539us 1 1 100.00
keymgr_sideload_kmac 2.340s 234.289us 1 1 100.00
keymgr_sideload_aes 3.230s 96.266us 1 1 100.00
keymgr_sideload_otbn 2.250s 156.093us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 2.420s 53.177us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 3.660s 111.912us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.850s 644.257us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 7.310s 453.037us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 4.480s 159.494us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 6.050s 418.197us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 5.020s 782.329us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.800s 18.995us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.880s 21.774us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.160s 421.730us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.160s 421.730us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.410s 62.610us 1 1 100.00
keymgr_csr_rw 0.950s 48.657us 1 1 100.00
keymgr_csr_aliasing 2.900s 831.145us 1 1 100.00
keymgr_same_csr_outstanding 1.970s 175.466us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.410s 62.610us 1 1 100.00
keymgr_csr_rw 0.950s 48.657us 1 1 100.00
keymgr_csr_aliasing 2.900s 831.145us 1 1 100.00
keymgr_same_csr_outstanding 1.970s 175.466us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 19.260s 3038.192us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 19.260s 3038.192us 1 1 100.00
keymgr_tl_intg_err 5.280s 245.748us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 6.880s 435.204us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 6.880s 435.204us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 6.880s 435.204us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 6.880s 435.204us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 3.350s 109.999us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 19.260s 3038.192us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 19.260s 3038.192us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 5.280s 245.748us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 6.880s 435.204us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 8.100s 1122.686us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 3.090s 132.793us 1 1 100.00
keymgr_csr_rw 0.950s 48.657us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 3.090s 132.793us 1 1 100.00
keymgr_csr_rw 0.950s 48.657us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 3.090s 132.793us 1 1 100.00
keymgr_csr_rw 0.950s 48.657us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 3.660s 111.912us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 4.480s 159.494us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 4.480s 159.494us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 3.090s 132.793us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.860s 299.189us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 19.260s 3038.192us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 19.260s 3038.192us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 19.260s 3038.192us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 1.800s 54.423us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 3.660s 111.912us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 19.260s 3038.192us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 19.260s 3038.192us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 19.260s 3038.192us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.800s 54.423us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.800s 54.423us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 19.260s 3038.192us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.800s 54.423us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 19.260s 3038.192us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 1.800s 54.423us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 9.630s 2571.340us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 67922118174514869126444634802313065483010787921857763945388684477938234672569 1379
UVM_INFO @ 2571340367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---