Simulation Results: kmac/masked

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.19 %
  • code
  • 69.99 %
  • assert
  • 97.75 %
  • func
  • 78.84 %
  • line
  • 96.31 %
  • branch
  • 90.86 %
  • cond
  • 85.80 %
  • toggle
  • 29.50 %
  • FSM
  • 47.47 %
Validation stages
V1
100.00%
V2
72.41%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 51.910s 18003.609us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.080s 131.853us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.040s 328.687us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 8.820s 1625.804us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.320s 264.822us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.740s 352.263us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.040s 328.687us 1 1 100.00
kmac_csr_aliasing 5.320s 264.822us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.860s 26.928us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.220s 24.852us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2431.690s 33044.776us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 46.150s 1659.047us 1 1 100.00
test_vectors 7 8 87.50
kmac_test_vectors_sha3_224 28.640s 4849.603us 1 1 100.00
kmac_test_vectors_sha3_256 26.870s 5941.432us 1 1 100.00
kmac_test_vectors_sha3_384 1641.780s 477914.845us 1 1 100.00
kmac_test_vectors_sha3_512 1.220s 55.610us 0 1 0.00
kmac_test_vectors_shake_128 2981.070s 274890.362us 1 1 100.00
kmac_test_vectors_shake_256 2265.280s 92975.601us 1 1 100.00
kmac_test_vectors_kmac 2.030s 194.647us 1 1 100.00
kmac_test_vectors_kmac_xof 1.980s 169.170us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 114.830s 24197.918us 1 1 100.00
app 0 1 0.00
kmac_app 4.430s 893.022us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 1.700s 732.463us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 4.570s 1591.472us 0 1 0.00
error 1 1 100.00
kmac_error 14.910s 1161.078us 1 1 100.00
key_error 0 1 0.00
kmac_key_error 1.030s 41.346us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 1.080s 7.718us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 1.010s 73.805us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 1.310s 88.999us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 1.240s 55.281us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.580s 103.300us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 276.370s 28782.110us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.790s 25.995us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.850s 17.365us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.620s 159.113us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.620s 159.113us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.080s 131.853us 1 1 100.00
kmac_csr_rw 1.040s 328.687us 1 1 100.00
kmac_csr_aliasing 5.320s 264.822us 1 1 100.00
kmac_same_csr_outstanding 1.530s 134.596us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.080s 131.853us 1 1 100.00
kmac_csr_rw 1.040s 328.687us 1 1 100.00
kmac_csr_aliasing 5.320s 264.822us 1 1 100.00
kmac_same_csr_outstanding 1.530s 134.596us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.690s 75.240us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.690s 75.240us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.690s 75.240us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.690s 75.240us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.480s 256.936us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 93.190s 19548.758us 1 1 100.00
kmac_tl_intg_err 3.870s 1474.100us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.870s 1474.100us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.580s 103.300us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 51.910s 18003.609us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 114.830s 24197.918us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.690s 75.240us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 93.190s 19548.758us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 93.190s 19548.758us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 93.190s 19548.758us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 51.910s 18003.609us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.580s 103.300us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 93.190s 19548.758us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 4.710s 243.666us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 51.910s 18003.609us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 38.840s 7791.497us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 6 test runs
kmac_sideload_invalid 30056253434582049533525902895543996391979288455773140531708049370459628175648 76
UVM_INFO @ 7717786 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app 94735931903040616589556544322623198829996672505833917396549998841724804589730 79
UVM_INFO @ 893021814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 68946650304762352190868969556570774467963964429018374465022213782281153357875 77
UVM_INFO @ 732463220 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 95135510341551237498125156749472131861595848892404731367460889089240562027431 78
UVM_INFO @ 1591471550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 6648232460533274883015887807867057876761805170723194845826665497390507793162 110
UVM_INFO @ 28782110352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 19448565770394939982380541588885220275051711327658462075388228116954235921082 255
UVM_INFO @ 7791496659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_key_error 37673469580843571091262321038090150102627257455507476305549705352490652656731 78
UVM_ERROR @ 41345842 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 41345842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 40341400883453712158997006997771948387519748986265940058757378902131807158652 78
UVM_ERROR @ 55280515 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 55280515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * 1 test run
kmac_test_vectors_sha3_512 71970991979489800714417407858845591515433302236258733841424405264380790708080 78
UVM_INFO @ 55609501 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 1 test run
kmac_mubi 63227292123576981197156433746013412986963534412115068561033475698447735040719 79
UVM_INFO @ 243666067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---