Simulation Results: kmac/unmasked

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.46 %
  • code
  • 66.18 %
  • assert
  • 96.35 %
  • func
  • 72.84 %
  • line
  • 92.84 %
  • branch
  • 87.05 %
  • cond
  • 82.51 %
  • toggle
  • 27.64 %
  • FSM
  • 40.88 %
Validation stages
V1
100.00%
V2
72.41%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 20.250s 2796.985us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.960s 22.003us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.040s 241.000us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 8.220s 3729.744us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 6.880s 450.863us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 2.150s 80.863us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.040s 241.000us 1 1 100.00
kmac_csr_aliasing 6.880s 450.863us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.760s 154.554us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.440s 55.061us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 508.790s 50507.630us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 345.370s 261515.567us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 2139.310s 197042.881us 1 1 100.00
kmac_test_vectors_sha3_256 1333.790s 103477.482us 1 1 100.00
kmac_test_vectors_sha3_384 876.440s 18810.912us 1 1 100.00
kmac_test_vectors_sha3_512 974.990s 242352.255us 1 1 100.00
kmac_test_vectors_shake_128 115.050s 13965.224us 1 1 100.00
kmac_test_vectors_shake_256 1314.040s 24750.667us 1 1 100.00
kmac_test_vectors_kmac 2.810s 749.765us 1 1 100.00
kmac_test_vectors_kmac_xof 1.700s 68.533us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 138.540s 20166.893us 1 1 100.00
app 0 1 0.00
kmac_app 10.320s 2431.660us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 0.910s 6.049us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 11.020s 2846.482us 0 1 0.00
error 0 1 0.00
kmac_error 16.460s 1598.624us 0 1 0.00
key_error 0 1 0.00
kmac_key_error 1.090s 48.022us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 0.770s 7.989us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 8.640s 230.252us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 9.340s 2937.982us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 0.930s 63.330us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.230s 166.693us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 4.510s 1214.539us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.910s 42.448us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.800s 22.588us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.150s 459.201us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.150s 459.201us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.960s 22.003us 1 1 100.00
kmac_csr_rw 1.040s 241.000us 1 1 100.00
kmac_csr_aliasing 6.880s 450.863us 1 1 100.00
kmac_same_csr_outstanding 1.720s 75.105us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.960s 22.003us 1 1 100.00
kmac_csr_rw 1.040s 241.000us 1 1 100.00
kmac_csr_aliasing 6.880s 450.863us 1 1 100.00
kmac_same_csr_outstanding 1.720s 75.105us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.290s 159.592us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.290s 159.592us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.290s 159.592us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.290s 159.592us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 4.740s 4264.229us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 67.400s 14678.180us 1 1 100.00
kmac_tl_intg_err 2.090s 116.915us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.090s 116.915us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.230s 166.693us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 20.250s 2796.985us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 138.540s 20166.893us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.290s 159.592us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 67.400s 14678.180us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 67.400s 14678.180us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 67.400s 14678.180us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 20.250s 2796.985us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.230s 166.693us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 67.400s 14678.180us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 16.160s 2138.930us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 20.250s 2796.985us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 4.700s 1664.838us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 6 test runs
kmac_app 19737299544409241383396421614801949610308111387037472815803924054675207602344 81
UVM_INFO @ 2431659600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 28069351133970985013694228908490012136160846735691077765740800318327902146368 77
UVM_INFO @ 6048617 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 107738875237174039070321451854610533898915410459168829516786506290708218589223 81
UVM_INFO @ 2846481801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_error 38535012392247699864747358826204829393678634811879208065097104752744664586456 90
UVM_INFO @ 1598623686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 46710930267766664831340884397115636096224114251094727961343613276669171384798 77
UVM_INFO @ 63329600 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 50620874968953247270025886066053557335992245405688305907339052752008155747257 81
UVM_INFO @ 1214539479 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 2 test runs
kmac_sideload_invalid 3119801705846716381021330613185446086322277680513731035896158644452536479454 79
UVM_ERROR @ 7989063 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 7989063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 79907759468808777244050134780490919286471843877562131545094184103268682567112 78
UVM_ERROR @ 48021533 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 48021533 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 2 test runs
kmac_mubi 27006626299137060407104480677709054228430084020132192236121632241791438325344 84
UVM_INFO @ 2138929504 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 34800317564461785470321306433452714809994165643424166421629623949957761105405 142
UVM_INFO @ 1664837551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---