Simulation Results: lc_ctrl/volatile_unlock_disabled

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.09 %
  • code
  • 84.10 %
  • assert
  • 94.69 %
  • func
  • 94.48 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 79.22 %
  • toggle
  • 84.03 %
  • FSM
  • 66.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.740s 39.877us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.060s 37.605us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.130s 21.243us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.250s 24.592us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 41.151us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.050s 51.146us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.130s 21.243us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 41.151us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.940s 295.473us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 10.800s 269.877us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.810s 14.519us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.630s 45.306us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.670s 527.728us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.130s 869.690us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.670s 527.728us 1 1 100.00
lc_ctrl_prog_failure 1.630s 45.306us 1 1 100.00
lc_ctrl_errors 6.130s 869.690us 1 1 100.00
lc_ctrl_security_escalation 7.490s 546.991us 1 1 100.00
lc_ctrl_jtag_state_failure 16.410s 4466.180us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.230s 432.568us 1 1 100.00
lc_ctrl_jtag_errors 20.360s 9933.324us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.710s 1456.541us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.440s 530.405us 1 1 100.00
lc_ctrl_jtag_prog_failure 9.230s 432.568us 1 1 100.00
lc_ctrl_jtag_errors 20.360s 9933.324us 1 1 100.00
lc_ctrl_jtag_access 6.900s 621.888us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 16.700s 4422.221us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.960s 89.169us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.330s 35.873us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 14.410s 12152.977us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.420s 750.306us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.070s 30.108us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.020s 202.022us 1 1 100.00
lc_ctrl_jtag_alert_test 1.380s 51.584us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.520s 3291.788us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.990s 47.125us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 221.700s 34618.560us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.350s 374.659us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.520s 203.177us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.520s 203.177us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.060s 37.605us 1 1 100.00
lc_ctrl_csr_rw 1.130s 21.243us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 41.151us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.560s 51.617us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.060s 37.605us 1 1 100.00
lc_ctrl_csr_rw 1.130s 21.243us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 41.151us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.560s 51.617us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.180s 122.787us 1 1 100.00
lc_ctrl_tl_intg_err 1.670s 213.550us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.670s 213.550us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 10.800s 269.877us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.670s 527.728us 1 1 100.00
lc_ctrl_sec_cm 6.180s 122.787us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.670s 527.728us 1 1 100.00
lc_ctrl_sec_cm 6.180s 122.787us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.670s 527.728us 1 1 100.00
lc_ctrl_sec_cm 6.180s 122.787us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.670s 527.728us 1 1 100.00
lc_ctrl_sec_cm 6.180s 122.787us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.670s 527.728us 1 1 100.00
lc_ctrl_sec_cm 6.180s 122.787us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.670s 527.728us 1 1 100.00
lc_ctrl_sec_cm 6.180s 122.787us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.670s 527.728us 1 1 100.00
lc_ctrl_sec_cm 6.180s 122.787us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.670s 527.728us 1 1 100.00
lc_ctrl_sec_cm 6.180s 122.787us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.490s 546.991us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.940s 295.473us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.440s 530.405us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.150s 1145.573us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 9.150s 1145.573us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 5.640s 814.023us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.800s 1447.006us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.800s 1447.006us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 59.270s 11602.011us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 41497977609282825912510157108848097483560338829064361267138897624496348977922 6977
UVM_INFO @ 11602010791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---