Simulation Results: lc_ctrl/volatile_unlock_enabled

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.38 %
  • code
  • 83.62 %
  • assert
  • 94.83 %
  • func
  • 92.70 %
  • line
  • 97.09 %
  • branch
  • 93.23 %
  • cond
  • 79.34 %
  • toggle
  • 83.04 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
93.33%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.650s 107.156us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.860s 22.229us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.870s 41.573us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.930s 60.011us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 34.360us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.580s 33.726us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.870s 41.573us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 34.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.270s 86.207us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 7.460s 417.712us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.800s 13.634us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.060s 292.167us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 11.940s 1670.444us 1 1 100.00
lc_errors 0 1 0.00
lc_ctrl_errors 5.490s 204.925us 0 1 0.00
security_escalation 5 7 71.43
lc_ctrl_state_failure 11.940s 1670.444us 1 1 100.00
lc_ctrl_prog_failure 2.060s 292.167us 1 1 100.00
lc_ctrl_errors 5.490s 204.925us 0 1 0.00
lc_ctrl_security_escalation 7.090s 1289.641us 1 1 100.00
lc_ctrl_jtag_state_failure 21.320s 1604.965us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.330s 777.089us 1 1 100.00
lc_ctrl_jtag_errors 24.280s 2281.192us 0 1 0.00
jtag_access 12 13 92.31
lc_ctrl_jtag_smoke 3.960s 1334.054us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.580s 848.065us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.330s 777.089us 1 1 100.00
lc_ctrl_jtag_errors 24.280s 2281.192us 0 1 0.00
lc_ctrl_jtag_access 4.040s 172.834us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 12.500s 3605.339us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.270s 435.003us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.120s 60.169us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.340s 1859.391us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.330s 2771.349us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.690s 95.906us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.330s 1064.597us 1 1 100.00
lc_ctrl_jtag_alert_test 0.930s 38.252us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.980s 159.001us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.950s 12.789us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 19.360s 1258.816us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.990s 242.089us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.180s 283.149us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.180s 283.149us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 22.229us 1 1 100.00
lc_ctrl_csr_rw 0.870s 41.573us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 34.360us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.530s 78.360us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.860s 22.229us 1 1 100.00
lc_ctrl_csr_rw 0.870s 41.573us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 34.360us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.530s 78.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.050s 904.687us 1 1 100.00
lc_ctrl_tl_intg_err 1.960s 61.922us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.960s 61.922us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 7.460s 417.712us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 11.940s 1670.444us 1 1 100.00
lc_ctrl_sec_cm 7.050s 904.687us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 11.940s 1670.444us 1 1 100.00
lc_ctrl_sec_cm 7.050s 904.687us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.940s 1670.444us 1 1 100.00
lc_ctrl_sec_cm 7.050s 904.687us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 11.940s 1670.444us 1 1 100.00
lc_ctrl_sec_cm 7.050s 904.687us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 11.940s 1670.444us 1 1 100.00
lc_ctrl_sec_cm 7.050s 904.687us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.940s 1670.444us 1 1 100.00
lc_ctrl_sec_cm 7.050s 904.687us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 11.940s 1670.444us 1 1 100.00
lc_ctrl_sec_cm 7.050s 904.687us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 11.940s 1670.444us 1 1 100.00
lc_ctrl_sec_cm 7.050s 904.687us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.090s 1289.641us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.270s 86.207us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.580s 848.065us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.390s 1264.835us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.390s 1264.835us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.070s 1639.114us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.610s 410.206us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 8.610s 410.206us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 55.320s 60738.415us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*]) 2 test runs
lc_ctrl_errors 37116737833252563890450400067298088488479223760986652307434669281973488156828 3219
UVM_INFO @ 204924659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
lc_ctrl_jtag_errors 1176149764304095039755145804290665505869774034846017517771161570207033941890 2639
UVM_INFO @ 2281191521 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 15490776936447372202312017288251955882935623429813093689877096611786198209880 10407
UVM_INFO @ 60738415063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---