Simulation Results: otbn

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.43 %
  • code
  • 86.28 %
  • assert
  • 90.55 %
  • func
  • 97.46 %
  • block
  • 99.30 %
  • line
  • 99.48 %
  • branch
  • 95.02 %
  • toggle
  • 84.43 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 11.000s 38.737us 1 1 100.00
single_binary 1 1 100.00
otbn_single 16.000s 148.749us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 21.000s 15.424us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 20.000s 24.707us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 23.000s 514.464us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 22.000s 19.966us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 23.000s 120.056us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 20.000s 24.707us 1 1 100.00
otbn_csr_aliasing 22.000s 19.966us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 97.000s 6727.367us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 28.000s 569.471us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 26.000s 73.465us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 57.000s 368.874us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 47.000s 1112.252us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 131.000s 2206.738us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 19.000s 95.117us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.196us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 8.000s 22.450us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 23.000s 40.519us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 15.095us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 8.000s 118.867us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 8.000s 118.867us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 21.000s 15.424us 1 1 100.00
otbn_csr_rw 20.000s 24.707us 1 1 100.00
otbn_csr_aliasing 22.000s 19.966us 1 1 100.00
otbn_same_csr_outstanding 4.000s 28.751us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 21.000s 15.424us 1 1 100.00
otbn_csr_rw 20.000s 24.707us 1 1 100.00
otbn_csr_aliasing 22.000s 19.966us 1 1 100.00
otbn_same_csr_outstanding 4.000s 28.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 18.000s 321.553us 1 1 100.00
otbn_dmem_err 22.000s 58.217us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 2.058s 0.000us 0 1 0.00
otbn_controller_ispr_rdata_err 24.000s 102.062us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 204.210us 1 1 100.00
otbn_urnd_err 5.000s 10.774us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 17.000s 35.215us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 8.000s 20.423us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 103.534us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
otbn_tl_intg_err 16.000s 100.551us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 24.000s 1031.669us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 11.000s 38.737us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 22.000s 58.217us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 18.000s 321.553us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 16.000s 100.551us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 19.000s 95.117us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 18.000s 321.553us 1 1 100.00
otbn_dmem_err 22.000s 58.217us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.196us 1 1 100.00
otbn_illegal_mem_acc 17.000s 35.215us 1 1 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 16.000s 148.749us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 18.000s 321.553us 1 1 100.00
otbn_dmem_err 22.000s 58.217us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.196us 1 1 100.00
otbn_illegal_mem_acc 17.000s 35.215us 1 1 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 19.000s 95.117us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 18.000s 321.553us 1 1 100.00
otbn_dmem_err 22.000s 58.217us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 10.196us 1 1 100.00
otbn_illegal_mem_acc 17.000s 35.215us 1 1 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 16.000s 148.749us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 26.000s 36.561us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 24.852us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 28.000s 139.006us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 28.000s 139.006us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 6.000s 44.886us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 14.000s 75.517us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 15.000s 45.143us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 15.000s 45.143us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 25.145us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 16.000s 148.749us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 16.000s 148.749us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 16.000s 148.749us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 47.000s 1112.252us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 16.000s 148.749us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 16.000s 148.749us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 24.000s 232.414us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 16.000s 148.749us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 181.000s 3174.501us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 135.000s 9490.174us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 117.337us 1 1 100.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 1 test run
otbn_alu_bignum_mod_err 54584008502447730332167710891322889545033303075695256615449702609635034520091 None
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 122, in _gen_loop_head
enc_bodysize, end_addr = self._pick_bodysize(insn, model.pc, program)
~~~~~~~~~~~~~~~~~~~^^^^^^^^^^^^^^^^^^^^^^^^^
File "/nightly/current_run/opentitan/hw/ip/otbn/dv/rig/rig/gens/bad_deep_loop.py", line 67, in _pick_bodysize
assert bodysize is not None
^^^^^^^^^^^^^^^^^^^^
AssertionError
ninja: build stopped: subcommand failed.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:52: pre_run] Error 1