Simulation Results: otp_ctrl

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.42 %
  • code
  • 78.72 %
  • assert
  • 94.82 %
  • func
  • 73.71 %
  • line
  • 88.49 %
  • branch
  • 83.22 %
  • cond
  • 90.38 %
  • toggle
  • 88.78 %
  • FSM
  • 42.71 %
Validation stages
V1
100.00%
V2
90.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 2.810s 814.730us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 5.800s 4181.987us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.390s 66.839us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.340s 183.321us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 7.420s 2258.222us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.750s 195.330us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.160s 424.900us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.340s 183.321us 1 1 100.00
otp_ctrl_csr_aliasing 4.750s 195.330us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.440s 135.809us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.120s 42.927us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 15.020s 1893.531us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 3.610s 536.315us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 7.210s 1951.217us 1 1 100.00
otp_ctrl_check_fail 7.980s 1413.408us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.810s 193.232us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 29.920s 4942.332us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 13.610s 1175.560us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 23.220s 10002.566us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.860s 404.492us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 21.410s 2745.408us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 12.350s 1068.775us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 14.190s 642.305us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 78.190s 8867.911us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.410s 79.706us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.600s 691.517us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.130s 334.458us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.130s 334.458us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.390s 66.839us 1 1 100.00
otp_ctrl_csr_rw 1.340s 183.321us 1 1 100.00
otp_ctrl_csr_aliasing 4.750s 195.330us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.310s 81.764us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.390s 66.839us 1 1 100.00
otp_ctrl_csr_rw 1.340s 183.321us 1 1 100.00
otp_ctrl_csr_aliasing 4.750s 195.330us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.310s 81.764us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
otp_ctrl_tl_intg_err 7.560s 649.078us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.560s 649.078us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 5.800s 4181.987us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 5.800s 4181.987us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.860s 404.492us 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.860s 404.492us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.860s 404.492us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.860s 404.492us 1 1 100.00
otp_ctrl_macro_errs 12.350s 1068.775us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.860s 404.492us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.860s 404.492us 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.860s 404.492us 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.860s 404.492us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.860s 404.492us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.860s 404.492us 1 1 100.00
otp_ctrl_macro_errs 12.350s 1068.775us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.860s 404.492us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.860s 404.492us 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 3.610s 536.315us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 7.980s 1413.408us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 29.920s 4942.332us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 29.920s 4942.332us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 29.920s 4942.332us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 29.920s 4942.332us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 29.920s 4942.332us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 5.800s 4181.987us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 29.920s 4942.332us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 5.800s 4181.987us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 109.280s 19289.566us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.810s 193.232us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 5.800s 4181.987us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 5.800s 4181.987us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 12.350s 1068.775us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.940s 3638.879us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 18.890s 9377.178us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_check_fail 63363842513106599921038711185331780663589101868037520078338188948720336374125 3725
UVM_INFO @ 1413408287 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 31519389321139484140338606077792711747645954136566378227530845195499752427676 6397
UVM_INFO @ 1068774687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 97140339093892398549630699392628678175092664676367590729312839143698990392937 3757
UVM_INFO @ 9377177607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---