Simulation Results: pwrmgr

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.01 %
  • code
  • 97.08 %
  • assert
  • 98.43 %
  • func
  • 98.52 %
  • line
  • 99.09 %
  • branch
  • 96.18 %
  • cond
  • 95.62 %
  • toggle
  • 98.49 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.630s 24.903us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.710s 30.391us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.690s 52.610us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.750s 778.702us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.980s 27.376us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.740s 51.167us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.690s 52.610us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 27.376us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.690s 107.422us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.690s 107.422us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.840s 29.964us 1 1 100.00
pwrmgr_lowpower_invalid 0.760s 63.172us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.650s 60.823us 1 1 100.00
pwrmgr_reset_invalid 0.780s 154.666us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.650s 60.823us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.720s 73.290us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.760s 84.433us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.730s 56.336us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.710s 540.173us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.670s 50.760us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 2.450s 865.963us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 2.450s 865.963us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 30.391us 1 1 100.00
pwrmgr_csr_rw 0.690s 52.610us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 27.376us 1 1 100.00
pwrmgr_same_csr_outstanding 0.780s 34.308us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 30.391us 1 1 100.00
pwrmgr_csr_rw 0.690s 52.610us 1 1 100.00
pwrmgr_csr_aliasing 0.980s 27.376us 1 1 100.00
pwrmgr_same_csr_outstanding 0.780s 34.308us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 0.940s 219.793us 1 1 100.00
pwrmgr_sec_cm 1.400s 682.484us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.400s 682.484us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.400s 682.484us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 0.940s 219.793us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.220s 894.697us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.720s 73.290us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.700s 954.641us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.800s 51.522us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.590s 33.408us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.400s 682.484us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.400s 682.484us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.400s 682.484us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.700s 54.198us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.640s 62.247us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.990s 240.001us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 52.610us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 52.610us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.710s 520.473us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 4.360s 18239.189us 0 1 0.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 110029977759465048230530220628532445267225235383391507251988558234939185003885 79
UVM_ERROR @ 520472556 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 520472556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all_with_rand_reset 59756921180797301351579957566667655002143526726984855834512432822787818125553 1550
UVM_INFO @ 18239189381 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---