Simulation Results: rom_ctrl/64kb

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.42 %
  • code
  • 97.13 %
  • assert
  • 97.53 %
  • func
  • 97.61 %
  • line
  • 99.46 %
  • branch
  • 99.64 %
  • cond
  • 97.92 %
  • toggle
  • 95.29 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.820s 642.847us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 11.960s 389.007us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.010s 650.886us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 8.730s 7062.634us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 6.560s 537.478us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.920s 427.651us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.010s 650.886us 1 1 100.00
rom_ctrl_csr_aliasing 6.560s 537.478us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.900s 315.451us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 5.830s 205.800us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.840s 2066.675us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 29.790s 4088.374us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 12.790s 384.005us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.720s 377.525us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.510s 956.090us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.510s 956.090us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.960s 389.007us 1 1 100.00
rom_ctrl_csr_rw 6.010s 650.886us 1 1 100.00
rom_ctrl_csr_aliasing 6.560s 537.478us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.370s 307.046us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.960s 389.007us 1 1 100.00
rom_ctrl_csr_rw 6.010s 650.886us 1 1 100.00
rom_ctrl_csr_aliasing 6.560s 537.478us 1 1 100.00
rom_ctrl_same_csr_outstanding 8.370s 307.046us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.890s 4870.116us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.740s 1443.367us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 470.270s 787.562us 1 1 100.00
rom_ctrl_tl_intg_err 100.210s 854.638us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 470.270s 787.562us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 470.270s 787.562us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.890s 4870.116us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.890s 4870.116us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.890s 4870.116us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.890s 4870.116us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.890s 4870.116us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 470.270s 787.562us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 470.270s 787.562us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.820s 642.847us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.820s 642.847us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.820s 642.847us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 100.210s 854.638us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.890s 4870.116us 1 1 100.00
rom_ctrl_kmac_err_chk 12.790s 384.005us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.890s 4870.116us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.890s 4870.116us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 115.890s 4870.116us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 22.740s 1443.367us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 470.270s 787.562us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 93.380s 12846.876us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 83541345671267800999999374838698780869039956986195175371567543414635129157263 79
UVM_INFO @ 2066675329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---