Simulation Results: rstmgr

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.44 %
  • code
  • 99.41 %
  • assert
  • 98.39 %
  • func
  • 97.51 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.82 %
  • toggle
  • 99.50 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.310s 283.320us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.120s 150.694us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.990s 78.405us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 7.900s 2464.508us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.840s 157.741us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.020s 136.364us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.990s 78.405us 1 1 100.00
rstmgr_csr_aliasing 1.840s 157.741us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.740s 113.989us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.450s 170.697us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.070s 108.997us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.280s 1094.669us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.280s 1094.669us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.280s 1094.669us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.280s 1094.669us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 18.280s 6861.381us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.730s 67.778us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.510s 144.499us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.510s 144.499us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.120s 150.694us 1 1 100.00
rstmgr_csr_rw 0.990s 78.405us 1 1 100.00
rstmgr_csr_aliasing 1.840s 157.741us 1 1 100.00
rstmgr_same_csr_outstanding 1.310s 252.694us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.120s 150.694us 1 1 100.00
rstmgr_csr_rw 0.990s 78.405us 1 1 100.00
rstmgr_csr_aliasing 1.840s 157.741us 1 1 100.00
rstmgr_same_csr_outstanding 1.310s 252.694us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 19.920s 16860.048us 1 1 100.00
rstmgr_tl_intg_err 2.560s 922.839us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 19.920s 16860.048us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 19.920s 16860.048us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.560s 922.839us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.880s 119.523us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 7.230s 2809.966us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.320s 302.458us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 19.920s 16860.048us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.990s 78.405us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.990s 78.405us 1 1 100.00