Simulation Results: rv_timer

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.79 %
  • code
  • 94.59 %
  • assert
  • 98.73 %
  • func
  • 97.06 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.69 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.790s 88.582us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.610s 15.737us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.600s 89.111us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.540s 50.012us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.790s 221.295us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.700s 38.908us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.600s 89.111us 1 1 100.00
rv_timer_csr_aliasing 0.790s 221.295us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.660s 278.543us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.830s 546.298us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 2.570s 2880.295us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 2.570s 2880.295us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 3.150s 2381.954us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.550s 17.961us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.550s 56.012us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.060s 75.485us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.060s 75.485us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 15.737us 1 1 100.00
rv_timer_csr_rw 0.600s 89.111us 1 1 100.00
rv_timer_csr_aliasing 0.790s 221.295us 1 1 100.00
rv_timer_same_csr_outstanding 0.660s 16.975us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.610s 15.737us 1 1 100.00
rv_timer_csr_rw 0.600s 89.111us 1 1 100.00
rv_timer_csr_aliasing 0.790s 221.295us 1 1 100.00
rv_timer_same_csr_outstanding 0.660s 16.975us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.730s 299.061us 1 1 100.00
rv_timer_tl_intg_err 1.250s 255.546us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.250s 255.546us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.720s 230.050us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.670s 423.200us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 49.820s 8441.016us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 33420713384646928492650195932938723006686846222654209287374552160408766426080 76
UVM_INFO @ 230050261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 99875094330399563050024933227255527152209642346596116109027380071880510012229 75
UVM_INFO @ 278542603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 76562917366405431033985676906786159262510443235137569692640573161104182004970 75
UVM_INFO @ 423199610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---