Simulation Results: spi_device/1r1w

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.43 %
  • code
  • 91.43 %
  • assert
  • 95.40 %
  • func
  • 66.47 %
  • line
  • 98.87 %
  • branch
  • 98.23 %
  • cond
  • 96.38 %
  • toggle
  • 74.30 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 292.330s 310926.206us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.040s 109.681us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.400s 39.714us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 19.750s 2344.891us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 6.410s 1233.781us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.970s 569.344us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.400s 39.714us 1 1 100.00
spi_device_csr_aliasing 6.410s 1233.781us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.790s 70.255us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.670s 76.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.830s 38.475us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.780s 1.335us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.750s 3.509us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 2.020s 120.431us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 2.020s 120.431us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 12.340s 105249.896us 1 1 100.00
spi_device_tpm_sts_read 0.680s 20.045us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 8.390s 3877.174us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 11.550s 12759.065us 1 1 100.00
spi_device_flash_all 94.500s 41893.100us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.710s 19065.942us 1 1 100.00
spi_device_flash_all 94.500s 41893.100us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 7.710s 19065.942us 1 1 100.00
spi_device_flash_all 94.500s 41893.100us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 94.500s 41893.100us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.180s 774.375us 1 1 100.00
spi_device_flash_all 94.500s 41893.100us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.180s 774.375us 1 1 100.00
spi_device_flash_all 94.500s 41893.100us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.180s 774.375us 1 1 100.00
spi_device_flash_all 94.500s 41893.100us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.180s 774.375us 1 1 100.00
spi_device_flash_all 94.500s 41893.100us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.180s 774.375us 1 1 100.00
spi_device_flash_all 94.500s 41893.100us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 1.980s 944.191us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 6.460s 5576.926us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 6.460s 5576.926us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 6.460s 5576.926us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 3.980s 280.115us 1 1 100.00
spi_device_read_buffer_direct 5.700s 3100.713us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 6.460s 5576.926us 1 1 100.00
spi_device_flash_all 94.500s 41893.100us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 94.500s 41893.100us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 94.500s 41893.100us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 3.770s 743.821us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 3.770s 743.821us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 47.450s 61858.471us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 292.330s 310926.206us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 15.230s 1579.236us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 0.840s 104.879us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.760s 43.246us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.810s 19.589us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.390s 158.541us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.390s 158.541us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.040s 109.681us 1 1 100.00
spi_device_csr_rw 1.400s 39.714us 1 1 100.00
spi_device_csr_aliasing 6.410s 1233.781us 1 1 100.00
spi_device_same_csr_outstanding 2.680s 147.503us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.040s 109.681us 1 1 100.00
spi_device_csr_rw 1.400s 39.714us 1 1 100.00
spi_device_csr_aliasing 6.410s 1233.781us 1 1 100.00
spi_device_same_csr_outstanding 2.680s 147.503us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.130s 320.349us 1 1 100.00
spi_device_tl_intg_err 12.480s 2786.278us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 12.480s 2786.278us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 59868409658944530792944678551086269714338703415449078232111916947564290871675 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1213300 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1213300 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[907])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:28) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 85688427930046362271240894401360187046196561973599549170426386629487103720510 76
UVM_ERROR @ 1016981 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x4f [1001111] vs 0x0 [0])
UVM_ERROR @ 1034981 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x249 [1001001001] vs 0x0 [0])
UVM_ERROR @ 1084981 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x1cc [111001100] vs 0x0 [0])
UVM_ERROR @ 1117981 ps: (spi_device_ram_cfg_vseq.sv:28) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x21e [1000011110] vs 0x0 [0])