Simulation Results: sram_ctrl/main

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.54 %
  • code
  • 95.71 %
  • assert
  • 98.10 %
  • func
  • 92.80 %
  • block
  • 96.10 %
  • line
  • 96.83 %
  • branch
  • 94.17 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 2804.711us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 31.316us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.418us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 215.602us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 45.059us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 4.000s 1394.182us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 14.418us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 45.059us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 114.000s 13155.226us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 56.000s 2768.003us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 5.000s 796.619us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 174.000s 4778.737us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 113.000s 4456.733us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 23.000s 7723.505us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 30.000s 33986.055us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 20.000s 14119.625us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 7.000s 699.945us 1 1 100.00
sram_ctrl_partial_access_b2b 136.000s 27354.789us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 722.526us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 1834.003us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 2652.625us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 9.000s 2277.648us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 3068.656us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 93.000s 34605.183us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 25.293us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 36.459us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 36.459us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 31.316us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.418us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 45.059us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 27.304us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 31.316us 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.418us 1 1 100.00
sram_ctrl_csr_aliasing 2.000s 45.059us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 27.304us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 7277.928us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 701.256us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 170.519us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 701.256us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 170.519us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 2277.648us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 9.000s 2277.648us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 14.418us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 20.000s 14119.625us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 14119.625us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 20.000s 14119.625us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 30.000s 33986.055us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 1398.699us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.000s 7277.928us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 3.000s 680.584us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 2804.711us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 2804.711us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 20.000s 14119.625us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 701.256us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 30.000s 33986.055us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 701.256us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 701.256us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 2804.711us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 701.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 6.000s 425.412us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 43787540180702410491645294962128288053801453005161366482607096052347972266740 86
UVM_INFO @ 722525714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 25727659559136407344696269640472260391256104328109482233797717993665410065189 86
UVM_INFO @ 1834002750 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 68047907498165397539306711733421482647223345332196281602095046925828105127685 86
UVM_INFO @ 2652625320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---