Simulation Results: sysrst_ctrl

 
15/07/2026 15:30:26 DVSim: v1.49.12 sha: 189b2b0 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.44 %
  • code
  • 91.85 %
  • assert
  • 91.38 %
  • func
  • 64.08 %
  • line
  • 96.45 %
  • branch
  • 97.00 %
  • cond
  • 94.03 %
  • toggle
  • 100.00 %
  • FSM
  • 71.79 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.110s 2108.478us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.050s 2487.323us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 2.680s 2402.330us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 4.650s 2349.942us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 7.040s 4017.178us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 6.260s 2032.818us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 14.390s 38390.220us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 9.850s 2855.077us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 7.020s 2045.819us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 6.260s 2032.818us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.850s 2855.077us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 67.360s 169735.822us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 8.940s 34132.164us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 4.170s 3707.987us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 4.790s 3120.061us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 3.620s 2513.861us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.420s 2258.747us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 2.210s 3329.421us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 4.980s 2608.225us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 0.920s 6902.458us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 6.870s 31511.647us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 15.590s 11492.659us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.270s 2047.756us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.180s 2020.270us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.230s 2325.348us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.230s 2325.348us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.040s 4017.178us 1 1 100.00
sysrst_ctrl_csr_rw 6.260s 2032.818us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.850s 2855.077us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.580s 9267.896us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 7.040s 4017.178us 1 1 100.00
sysrst_ctrl_csr_rw 6.260s 2032.818us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.850s 2855.077us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 5.580s 9267.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 62.050s 42148.883us 1 1 100.00
sysrst_ctrl_tl_intg_err 16.030s 43084.755us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 16.030s 43084.755us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.680s 8437.680us 1 1 100.00