Simulation Results: adc_ctrl

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.28 %
  • code
  • 93.74 %
  • assert
  • 92.22 %
  • func
  • 12.89 %
  • line
  • 98.86 %
  • branch
  • 97.40 %
  • cond
  • 86.89 %
  • toggle
  • 99.05 %
  • FSM
  • 86.49 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 9.320s 5858.577us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 0.950s 788.003us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.800s 649.139us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 41.850s 26676.711us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.920s 1177.217us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.320s 420.716us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.800s 649.139us 1 1 100.00
adc_ctrl_csr_aliasing 1.920s 1177.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.800s 455.417us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.160s 421.558us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.880s 292.393us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.280s 523.351us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.780s 365.594us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.740s 336.881us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.690s 483.855us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.820s 459.456us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 1.800s 4507.780us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 44.930s 31307.539us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 35.340s 100185.113us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.620s 615.194us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.970s 353.484us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.860s 340.855us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.560s 1077.475us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.560s 1077.475us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.950s 788.003us 1 1 100.00
adc_ctrl_csr_rw 0.800s 649.139us 1 1 100.00
adc_ctrl_csr_aliasing 1.920s 1177.217us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.570s 2723.979us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.950s 788.003us 1 1 100.00
adc_ctrl_csr_rw 0.800s 649.139us 1 1 100.00
adc_ctrl_csr_aliasing 1.920s 1177.217us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.570s 2723.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.330s 8345.243us 1 1 100.00
adc_ctrl_tl_intg_err 2.500s 4632.552us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.500s 4632.552us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 0.950s 629.088us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 76756373331627537459963570319011061199267704612686865656344534597821080017582 386
UVM_INFO @ 455416607 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 11236376256153261152781672663383817896589064347214828463455335051035747369386 386
UVM_INFO @ 421557505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 71228048483479382163932706940053253439340180089628489249115131480275112090666 386
UVM_INFO @ 292393131 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 90014365483814353955474288459629340868019299263686375556081242076327998992762 386
UVM_INFO @ 523350964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 10623678073555528808979959011884065388446994343917039608003210915546782188399 386
UVM_INFO @ 365593741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 110930284826130031587923878963376054248469884106687344250405708180570523559667 386
UVM_INFO @ 336881454 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 25328723176019616738248770510345070124862177643811492096374021128869585916337 386
UVM_INFO @ 459455964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 19375237950102271012541320882839723681512149324706670208694429900986596029089 386
UVM_INFO @ 483855262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 94678611442424084703036584042701402157997384078900016004903314406905587049321 399
UVM_INFO @ 629087572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 99984834111130188168726617737884019503233645577101755009121362033259757576454 387
UVM_INFO @ 615193554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---