Simulation Results

Simulation Results: chip

16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
74.68 %

code
83.73 %

assert
97.49 %

func
42.81 %

line
94.11 %

branch
92.41 %

cond
88.35 %

toggle
86.62 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		74.01%
V2S		100.00%
V3		61.54%
unmapped		63.64%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	166.200s	2947.078us	1	1	100.00
	chip_sw_example_rom	78.450s	1874.168us	1	1	100.00
	chip_sw_example_manufacturer	145.790s	3139.369us	1	1	100.00
	chip_sw_example_concurrency	181.130s	2536.123us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	276.670s	6437.480us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	197.010s	4208.658us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	2521.270s	32117.084us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	4104.060s	30530.571us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	427.530s	7232.326us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	4104.060s	30530.571us	1	1	100.00
	chip_csr_rw	197.010s	4208.658us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	5.490s	50.267us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	332.260s	4313.756us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	332.260s	4313.756us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	332.260s	4313.756us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	438.560s	4657.438us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	438.560s	4657.438us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	383.020s	5104.302us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	410.280s	4094.684us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	390.110s	4410.435us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	890.350s	7739.685us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1070.640s	8157.705us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	282.640s	3821.058us	1	1	100.00

205/277 passed

74.01 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	265.810s	5401.683us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	265.810s	5401.683us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				0	1	0.00
	chip_sw_sleep_pin_mio_dio_val	171.940s	3097.066us	0	1	0.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	200.080s	3372.869us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	151.940s	2789.729us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	76.500s	3125.784us	1	1	100.00
	chip_tap_straps_testunlock0	279.680s	5395.315us	1	1	100.00
	chip_tap_straps_rma	282.130s	5617.609us	1	1	100.00
	chip_tap_straps_prod	95.350s	2106.329us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	562.120s	6444.523us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	562.120s	6444.523us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	626.310s	8915.365us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	729.520s	10526.518us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	347.770s	3777.456us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	616.560s	5895.513us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3989.610s	18838.383us	1	1	100.00
	chip_sw_aes_enc_jitter_en	151.320s	3087.997us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	760.610s	7513.699us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	163.800s	2931.362us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1335.450s	10006.402us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	178.460s	2712.711us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	366.530s	4516.355us	1	1	100.00
	chip_sw_clkmgr_jitter	189.570s	2920.101us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	177.930s	2921.305us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	429.190s	6040.973us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	272.740s	5426.973us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	150.100s	3318.857us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	272.740s	5426.973us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	154.890s	3731.451us	1	1	100.00
	chip_sw_aes_smoketest	145.850s	2991.520us	1	1	100.00
	chip_sw_aon_timer_smoketest	216.840s	3470.598us	1	1	100.00
	chip_sw_clkmgr_smoketest	182.140s	3234.444us	1	1	100.00
	chip_sw_csrng_smoketest	199.110s	3335.919us	1	1	100.00
	chip_sw_entropy_src_smoketest	1069.890s	7888.596us	1	1	100.00
	chip_sw_gpio_smoketest	201.780s	3213.553us	1	1	100.00
	chip_sw_hmac_smoketest	186.370s	3176.007us	1	1	100.00
	chip_sw_kmac_smoketest	173.600s	2823.413us	1	1	100.00
	chip_sw_otbn_smoketest	1225.960s	9176.436us	1	1	100.00
	chip_sw_pwrmgr_smoketest	292.830s	6302.951us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	378.410s	6632.803us	1	1	100.00
	chip_sw_rv_plic_smoketest	189.290s	2751.843us	1	1	100.00
	chip_sw_rv_timer_smoketest	149.760s	3243.829us	1	1	100.00
	chip_sw_rstmgr_smoketest	134.270s	2963.403us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	193.210s	3473.263us	1	1	100.00
	chip_sw_uart_smoketest	151.850s	2863.189us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	204.780s	3154.781us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	288.970s	4064.693us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	7745.510s	60129.936us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3106.690s	14662.092us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	22.998s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	1083.840s	14164.367us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	666.690s	14757.345us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	6844.120s	52643.364us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7281.890s	55447.320us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	142.000s	3117.233us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	142.000s	3117.233us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	4104.060s	30530.571us	1	1	100.00
	chip_same_csr_outstanding	1814.630s	24673.587us	1	1	100.00
	chip_csr_hw_reset	276.670s	6437.480us	1	1	100.00
	chip_csr_rw	197.010s	4208.658us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	4104.060s	30530.571us	1	1	100.00
	chip_same_csr_outstanding	1814.630s	24673.587us	1	1	100.00
	chip_csr_hw_reset	276.670s	6437.480us	1	1	100.00
	chip_csr_rw	197.010s	4208.658us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	6.100s	138.137us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.110s	36.858us	1	1	100.00
	xbar_smoke_large_delays	47.900s	7817.062us	1	1	100.00
	xbar_smoke_slow_rsp	45.590s	5556.844us	1	1	100.00
	xbar_random_zero_delays	18.470s	247.002us	1	1	100.00
	xbar_random_large_delays	207.600s	35972.793us	1	1	100.00
	xbar_random_slow_rsp	157.430s	18782.638us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	6.850s	143.353us	1	1	100.00
	xbar_error_and_unmapped_addr	14.380s	209.629us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	44.400s	1914.716us	1	1	100.00
	xbar_error_and_unmapped_addr	14.380s	209.629us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	17.680s	536.901us	1	1	100.00
	xbar_access_same_device_slow_rsp	200.240s	24943.105us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	6.050s	69.407us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	47.120s	823.846us	1	1	100.00
	xbar_stress_all_with_error	108.610s	2220.654us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	324.820s	3449.403us	1	1	100.00
	xbar_stress_all_with_reset_error	289.520s	6695.493us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3106.690s	14662.092us	1	1	100.00
rom_e2e_shutdown_output				0	1	0.00
	rom_e2e_shutdown_output	375.540s	6308.468us	0	1	0.00
rom_e2e_shutdown_exception_c				0	1	0.00
	rom_e2e_shutdown_exception_c	426.380s	5334.627us	0	1	0.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	136.570s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	21.368s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	23.437s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	8.950s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	7.987s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	43.367s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	23.730s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	11.580s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	26.323s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	18.659s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	121.706s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	30.816s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	29.056s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	31.428s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	49.163s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	19.040s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	18.120s	10.360us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	19.010s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	22.040s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	26.310s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.230s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	20.010s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	22.450s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.770s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	18.000s	10.360us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	19.110s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.840s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	19.150s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	23.000s	10.380us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	22.920s	10.140us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	58.614s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	102.690s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	66.753s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	70.951s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	7.444s	0.000us	0	1	0.00
rom_e2e_keymgr_init				1	3	33.33
	rom_e2e_keymgr_init_rom_ext_meas	5952.120s	29226.451us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	3095.590s	16033.223us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	3306.080s	16671.850us	0	1	0.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3327.440s	15559.836us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3290.550s	34623.681us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3290.550s	34623.681us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	190.980s	2747.111us	1	1	100.00
	chip_sw_aes_enc_jitter_en	151.320s	3087.997us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	144.140s	2889.951us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	166.540s	2949.189us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1586.400s	12214.645us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	194.440s	3401.544us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	441.940s	5125.647us	1	1	100.00
chip_sw_all_escalation_resets				0	1	0.00
	chip_sw_all_escalation_resets	206.870s	3126.848us	0	1	0.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	468.210s	5231.540us	1	1	100.00
	chip_plic_all_irqs_10	230.090s	3570.872us	1	1	100.00
	chip_plic_all_irqs_20	376.810s	4122.461us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	226.850s	3380.475us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1246.850s	13665.370us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	230.000s	4299.440us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	163.980s	3376.071us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.136s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1281.920s	9973.224us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	882.450s	7326.140us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	752.390s	7666.771us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	8044.810s	254685.415us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	219.230s	3990.145us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	292.830s	6302.951us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	219.230s	3990.145us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	443.730s	8538.155us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	443.730s	8538.155us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	298.230s	8021.029us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	416.050s	5400.697us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	623.490s	6046.294us	1	1	100.00
	chip_sw_aes_idle	166.540s	2949.189us	1	1	100.00
	chip_sw_hmac_enc_idle	191.700s	3479.180us	1	1	100.00
	chip_sw_kmac_idle	188.150s	3626.200us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	259.600s	3941.573us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	295.200s	4851.684us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	315.210s	5235.527us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	308.900s	5014.402us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	701.230s	10573.409us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	390.620s	4594.474us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	395.970s	4411.418us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	409.540s	4095.127us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	364.490s	4908.142us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	391.040s	3629.261us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	367.430s	4394.903us	1	1	100.00
	chip_sw_ast_clk_outputs	626.310s	8915.365us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	374.010s	5171.685us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	409.540s	4095.127us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	364.490s	4908.142us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	347.770s	3777.456us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	616.560s	5895.513us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3989.610s	18838.383us	1	1	100.00
	chip_sw_aes_enc_jitter_en	151.320s	3087.997us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	760.610s	7513.699us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	163.800s	2931.362us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1335.450s	10006.402us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	178.460s	2712.711us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	366.530s	4516.355us	1	1	100.00
	chip_sw_clkmgr_jitter	189.570s	2920.101us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	141.490s	3232.425us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	406.940s	4943.993us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	602.110s	7525.398us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4414.120s	25082.955us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	180.510s	3287.515us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	201.130s	3813.110us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	627.450s	7051.061us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	185.300s	3035.871us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	405.850s	5786.070us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1230.270s	23333.715us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	1795.460s	15119.276us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	626.310s	8915.365us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	370.560s	4626.154us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	270.420s	3600.234us	1	1	100.00
chip_sw_clkmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	206.870s	3126.848us	0	1	0.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	1281.920s	9973.224us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	1998.760s	24069.561us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	372.140s	4568.791us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	502.420s	7561.422us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	178.820s	3478.327us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	2262.270s	13716.265us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	137.790s	2763.376us	1	1	100.00
	chip_sw_edn_entropy_reqs	639.850s	7124.051us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	137.790s	2763.376us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	1998.760s	24069.561us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	144.580s	2944.254us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1500.770s	26052.090us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	527.470s	5838.687us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	616.560s	5895.513us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	369.100s	4083.581us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	347.770s	3777.456us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3395.480s	42172.774us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1500.770s	26052.090us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	225.530s	3597.255us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1607.140s	11768.772us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	142.710s	3364.471us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3395.480s	42172.774us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	142.710s	3364.471us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	142.710s	3364.471us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	142.710s	3364.471us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	142.710s	3364.471us	0	1	0.00
chip_sw_flash_lc_escalate_en				0	1	0.00
	chip_sw_all_escalation_resets	206.870s	3126.848us	0	1	0.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	261.510s	10128.778us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	587.340s	5524.529us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	532.000s	5801.589us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	532.000s	5801.589us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	189.110s	2714.928us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	163.800s	2931.362us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	191.700s	3479.180us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1565.000s	11839.407us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1895.380s	12018.399us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	370.460s	4434.681us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	372.210s	4552.452us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	319.820s	4043.046us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	304.840s	3706.692us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1607.140s	11768.772us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1335.450s	10006.402us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1656.000s	13185.187us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1586.400s	12214.645us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	5127.830s	20018.309us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	185.630s	3409.768us	1	1	100.00
	chip_sw_kmac_mode_kmac	204.610s	3418.641us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	178.460s	2712.711us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1607.140s	11768.772us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	326.380s	7051.298us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	157.170s	2778.569us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	727.650s	6383.843us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	188.150s	3626.200us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	441.940s	5125.647us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	76.500s	3125.784us	1	1	100.00
	chip_tap_straps_rma	282.130s	5617.609us	1	1	100.00
	chip_tap_straps_prod	95.350s	2106.329us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	177.820s	2448.689us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	326.380s	7051.298us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	326.380s	7051.298us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	326.380s	7051.298us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1079.290s	8924.491us	1	1	100.00
chip_sw_lc_ctrl_broadcast				19	22	86.36
	chip_sw_flash_ctrl_lc_rw_en	142.710s	3364.471us	0	1	0.00
	chip_sw_flash_rma_unlocked	3395.480s	42172.774us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	211.420s	3427.365us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	423.700s	5990.190us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	643.440s	6537.064us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	509.530s	7594.136us	0	1	0.00
	chip_sw_lc_ctrl_transition	326.380s	7051.298us	1	1	100.00
	chip_sw_keymgr_key_derivation	1607.140s	11768.772us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	375.170s	9890.095us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	566.710s	8300.179us	1	1	100.00
	chip_prim_tl_access	261.510s	10128.778us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	374.010s	5171.685us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	390.620s	4594.474us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	395.970s	4411.418us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	409.540s	4095.127us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	364.490s	4908.142us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	391.040s	3629.261us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	367.430s	4394.903us	1	1	100.00
	chip_tap_straps_dev	76.500s	3125.784us	1	1	100.00
	chip_tap_straps_rma	282.130s	5617.609us	1	1	100.00
	chip_tap_straps_prod	95.350s	2106.329us	1	1	100.00
	chip_rv_dm_lc_disabled	214.200s	5650.250us	0	1	0.00
chip_lc_scrap				2	4	50.00
	chip_sw_lc_ctrl_rma_to_scrap	170.800s	3325.557us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	92.520s	3224.629us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	704.060s	26499.047us	0	1	0.00
	chip_sw_lc_ctrl_rand_to_scrap	1902.780s	27296.050us	0	1	0.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1429.380s	33254.565us	1	1	100.00
	chip_rv_dm_lc_disabled	214.200s	5650.250us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	759.020s	10544.867us	0	1	0.00
	chip_sw_lc_walkthrough_prod	577.130s	7722.463us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	712.300s	9694.899us	1	1	100.00
	chip_sw_lc_walkthrough_rma	332.040s	7341.986us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1429.380s	33254.565us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	53.660s	2009.488us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	61.930s	2180.964us	1	1	100.00
	rom_volatile_raw_unlock	125.439s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3946.700s	16784.583us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3989.610s	18838.383us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	623.490s	6046.294us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	623.490s	6046.294us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	623.490s	6046.294us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	328.560s	3842.900us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	326.380s	7051.298us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1500.770s	26052.090us	1	1	100.00
	chip_sw_otbn_mem_scramble	328.560s	3842.900us	1	1	100.00
	chip_sw_keymgr_key_derivation	1607.140s	11768.772us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	351.690s	5702.652us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	150.050s	3382.095us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1500.770s	26052.090us	1	1	100.00
	chip_sw_otbn_mem_scramble	328.560s	3842.900us	1	1	100.00
	chip_sw_keymgr_key_derivation	1607.140s	11768.772us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	351.690s	5702.652us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	150.050s	3382.095us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	326.380s	7051.298us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	335.430s	5465.855us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	177.820s	2448.689us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	211.420s	3427.365us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	423.700s	5990.190us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	643.440s	6537.064us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	509.530s	7594.136us	0	1	0.00
	chip_sw_lc_ctrl_transition	326.380s	7051.298us	1	1	100.00
	chip_prim_tl_access	261.510s	10128.778us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	261.510s	10128.778us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	744.160s	7544.910us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	71.880s	2658.943us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	1440.870s	29382.836us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	233.160s	7724.313us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	301.360s	7942.255us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	381.580s	8328.316us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	788.790s	20924.576us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				0	2	0.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	378.980s	11112.681us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	443.730s	8538.155us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	703.250s	12400.835us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	407.040s	5648.006us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	71.880s	2658.943us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	253.870s	4293.661us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1951.430s	34121.452us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	343.080s	6518.798us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	167.250s	3174.152us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	193.900s	5314.577us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	716.800s	6771.908us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1178.200s	13518.616us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1465.890s	23050.687us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	159.460s	3046.219us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	206.870s	3126.848us	0	1	0.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	375.170s	9890.095us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	375.170s	9890.095us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	1178.200s	13518.616us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	193.900s	5314.577us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	407.040s	5648.006us	1	1	100.00
	chip_sw_pwrmgr_smoketest	292.830s	6302.951us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	313.920s	5591.664us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	475.800s	5889.412us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	267.220s	4198.783us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1246.850s	13665.370us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	163.810s	3265.659us	1	1	100.00
chip_sw_rstmgr_escalation_reset				0	1	0.00
	chip_sw_all_escalation_resets	206.870s	3126.848us	0	1	0.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	882.450s	7326.140us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	474.590s	5484.733us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	514.690s	4845.160us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	197.960s	2832.878us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	150.050s	3382.095us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	475.800s	5889.412us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	475.800s	5889.412us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	153.820s	2723.093us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	1207.250s	17181.764us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	891.440s	13696.546us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	313.920s	5591.664us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	174.130s	3102.370us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	1449.120s	13227.919us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	282.130s	5617.609us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	214.200s	5650.250us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	468.210s	5231.540us	1	1	100.00
	chip_plic_all_irqs_10	230.090s	3570.872us	1	1	100.00
	chip_plic_all_irqs_20	376.810s	4122.461us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	139.530s	2281.327us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	193.990s	3096.166us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3106.690s	14662.092us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	277.110s	4408.313us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	206.300s	2935.526us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	231.880s	2994.220us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	202.320s	3304.968us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	351.690s	5702.652us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	366.530s	4516.355us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	487.340s	9019.095us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	436.930s	7825.361us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	566.710s	8300.179us	1	1	100.00
chip_sw_sram_lc_escalation				1	2	50.00
	chip_sw_all_escalation_resets	206.870s	3126.848us	0	1	0.00
	chip_sw_data_integrity_escalation	562.120s	6444.523us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	716.800s	6771.908us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1056.900s	22965.642us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	191.370s	3615.867us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	260.940s	3588.513us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	304.310s	4313.481us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1056.900s	22965.642us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1056.900s	22965.642us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2562.930s	20224.434us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2562.930s	20224.434us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	319.820s	7149.350us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3290.550s	34623.681us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	187.630s	2818.051us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	184.740s	3614.517us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	290.630s	3682.622us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	318.630s	4085.881us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	920.200s	8351.336us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5386.030s	31292.171us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1865.230s	12429.717us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	147.030s	2931.583us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	177.420s	3148.106us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	129.260s	2543.038us	1	1	100.00

16/26 passed

61.54 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9244.840s	68797.595us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1141.000s	6693.221us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	173.950s	5122.690us	0	1	0.00
	rom_e2e_jtag_debug_dev	161.050s	3423.904us	0	1	0.00
	rom_e2e_jtag_debug_rma	182.870s	5088.338us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	76.830s	2620.597us	0	1	0.00
	rom_e2e_jtag_inject_dev	71.560s	2576.437us	0	1	0.00
	rom_e2e_jtag_inject_rma	63.860s	2265.665us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	116.875s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	250.940s	3188.183us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	345.220s	3173.357us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	755.320s	4704.312us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1354.350s	9333.132us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	225.560s	2461.236us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	537.060s	5514.890us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	73.700s	2344.289us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	208.970s	3453.628us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	237.420s	6143.687us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	282.910s	4996.098us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1178.200s	13518.616us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	173.950s	5122.690us	0	1	0.00
	rom_e2e_jtag_debug_dev	161.050s	3423.904us	0	1	0.00
	rom_e2e_jtag_debug_rma	182.870s	5088.338us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	405.010s	6016.865us	1	1	100.00
chip_sw_plic_alerts				0	1	0.00
	chip_sw_all_escalation_resets	206.870s	3126.848us	0	1	0.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5445.350s	38390.646us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5445.350s	38390.646us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	162.090s	3011.276us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	438.560s	4657.438us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	2976.360s	19090.732us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	203.580s	3586.740us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	21.080s	10.240us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	6.620s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	146.580s	2647.785us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	169.440s	3513.037us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	277.270s	3557.934us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	9.202s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	180.630s	2952.731us	1	1	100.00
	ate_bootstrap_flash_erase	530.110s	10010.240us	0	1	0.00
	ate_bootstrap_one_frame	6314.260s	43039.339us	1	1	100.00
	ate_bootstrap_disjoint	9500.920s	78936.608us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	111216627034761043075839655864372398882702773821869900822937237848007742951329	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	21618454602281796940436139284284440182682392216236274106886489012723721369030	None	Another command (pid=574925) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=598028) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=593385) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	93356767973920474718468062705472658344827327007860416161194948817101230494143	None	Another command (pid=630334) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=649926) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=642732) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	86498727722413729796489270720325038607276145292225292554972552375826215988980	None	Another command (pid=662994) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=628284) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=648098) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	5021903345489000726999660927818494159773951460557429149723507918012145797707	None	Another command (pid=640412) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=634750) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=643029) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	35550731854908272168297142195648969364753131999820607895777267914407053299166	None	---- STDERR ---- Another command (pid=634750) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=643029) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	42459198649087973290274743726925506913583620706026960610602753586293570685457	None	---- STDERR ---- Another command (pid=381832) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	93782538241866490013931731855311392583024174338542392199211527801362970592774	None	Another command (pid=621041) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=432621) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=623251) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	72968802352952682584228511809114156397452988186827697351007640338369986408106	None	Another command (pid=580991) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=580380) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=574925) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	53662639469926135440806412792720656685491335353292159039280116285628657194533	None	Another command (pid=604465) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=645805) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=663243) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	114364582667098787589079619070112107090473220867471015473753392760858232695604	None	Another command (pid=640412) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=634750) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=643029) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	94998836035613667727118208620532210336304615507216434360090690108729489201822	None	Another command (pid=470242) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=470627) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=471673) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	87157712868615124785023117645872922246621279721417723867329415996727687514984	None	Another command (pid=608387) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=622274) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=628861) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	75229101277485400228181051937307488121572011896883573720243831229422582548954	None	---- STDERR ---- Another command (pid=600357) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	12916965645969222955781207893909899800758792466190379568646502797221297636200	None	---- STDERR ---- Another command (pid=633305) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=602844) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	48686908233992484588080007064471996211827466860449836000889271259052122501588	None	Another command (pid=676452) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=686170) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=674199) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	36582911345264143703050549525498549043861446785022947563153599750181573586114	None	Another command (pid=448485) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=425837) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=463942) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	29190803873868359570305113376445725520660664193251268230454227929214480568327	None	Another command (pid=643029) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=640734) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=579408) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	97085655707351602219888703351691561438189846495435986876847243179910888658500	None	Another command (pid=471673) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=473304) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=478851) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	12864380610905187850665505388974827792208248140727298983952331978127795954296	None	Another command (pid=578169) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=582283) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=581972) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	79794599650872341978912433706132003713889921378051096448378181934809762062422	None	---- STDERR ---- Another command (pid=478851) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	61926858295910326806367786054601658636838195027955017960901297218468022130924	None	Another command (pid=503046) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=606693) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=600666) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	78982352586983576046596424426365212138100698336792685434250647493740710060651	None	Another command (pid=381832) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=406545) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=448485) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	35502451369807012677403502722581445630455976719541130593826220005125520630087	None	Another command (pid=446225) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=455460) is running. Waiting for it to complete on the server (server_pid=257362)... Another command (pid=465138) is running. Waiting for it to complete on the server (server_pid=257362)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				6 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	108213606639313369605502094902477208127930886539462358547048426004355790400942	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	4884466545700065525811400713998957697815814680235663267148522795416397643379	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	114442582711526224071277742993790177714144957181081220957907034581513919957991	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	1825666469166317816106039640315263766476628028008425935123970524247215063597	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	80124709586886473872525432324700944818300132095897975133292349407239217758727	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	87145245031093374340966904895122896908632572883870954478174072779611837203181	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	15750420833223824704655135532246862569202048154964845223047343974490865224943	367	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	5428601699671947655787456917041305644829056383225410264800921453771820095502	368	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	110141716322994660394033798339800137687891904796212985662698002264437085758095	366	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	20401057131510502137314607701919174319183656492436029521952274465200627086612	327	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19810925444581035629030246049583282120813222754720743458810203534605136991742	327	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	67976443221666230034876150772198352681687341721903167654058632443702649816210	326	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				5 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	94888751525764959694640571086305657718493661347525269030401246143732638954895	315	UVM_ERROR @ 5314.577000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 5314.577000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	77262090712349342736087012714014278296444498896141670582614504964247418949582	327	UVM_ERROR @ 11112.681000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 11112.681000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	49486801008461058212072535124503526890936973589295850394519996674011665041506	325	UVM_ERROR @ 7942.255000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7942.255000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	80180614858313593386341191955347946145180545760223373297586144467171058368012	431	UVM_ERROR @ 34121.452500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 34121.452500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	17609173803958025156084105144113973731570396582724755305785533009452586930388	319	UVM_ERROR @ 8538.155000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 8538.155000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	104253957293999064300796036526530135653588552434393971182301627915220215393637	369	UVM_INFO @ 10544.866910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	42688474373216710106072808068139548805169776155652200687712933541704285385459	369	UVM_INFO @ 7722.463390 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	32056356854786431564572186763274581915565351938745025551104592948646810517986	341	UVM_INFO @ 7341.986232 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	76924231706872389586863766826681013225154048697314232024990818312365424346191	326	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	48088093534904662849938061694619674778148507415775289281283039585875890812007	327	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	1781756441174776050195463634092120490557770651270382532885713582204214584841	326	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_scrap_vseq] max attempt reached to get lc status LcExtClockSwitched!				2 test runs
	chip_sw_lc_ctrl_test_locked0_to_scrap	105595133491449956034526205033687178185226727889034832306575338775651200145845	302	UVM_INFO @ 26499.046799 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_ctrl_rand_to_scrap	80187242391075081943128519850370170244392233635519587427944591750174737026706	313	UVM_INFO @ 27296.049985 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				2 test runs
	chip_sw_hmac_multistream	108855329314356606523297511133936867678417342301591558467866615321734356529639	358	UVM_INFO @ 12018.399113 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	83670232359630099728959924336547643102727070813891665388772384632925590711360	336	UVM_INFO @ 20018.309131 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	75499358481006862195635501149866085520250725862637408054720681054883814046259	362	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	89296650435710658694405052877761980206289752956016948456354739683888547006647	327	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	17371511350826471101177097382537495222586042398555670019688346868844497701591	363	UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	13887462448970288134592047936036461429344556352627119238604078773392071090199	328	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(sw/device/tests/sim_dv/all_escalation_resets_test.c:631)] CHECK-fail: Unexpected mtval: expected , got				1 test run
	chip_sw_all_escalation_resets	62977642045032674809452746613135776428883199346104110712560634871545821407548	317	UVM_INFO @ 3126.848231 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	52414539232825359524963238238324421487139759511004770774650084344380966329903	301	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [] vs xz [z]) for MIO[*]				1 test run
	chip_sw_sleep_pin_mio_dio_val	30499697630569405190745810001854985673123615050297745118991306592267228627638	451	UVM_INFO @ 3097.066000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch				1 test run
	chip_sw_spi_device_pass_through_collision	3715950535171091322443027570839147269506587990741328079755162319443852231949	329	host_rsp: ------------------------------------------------------------------------- Name Type Size Value -------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	107689362087185668185190249566416215089399556296071064688654238121529409860801	309	UVM_INFO @ 3364.470708 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	34525321305374496420559520503260929657528822170062885112494458807594092789180	342	UVM_INFO @ 7594.135608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	97126290189340662330437658115822894519908041323697969895148118754184012585737	316	UVM_ERROR @ 3453.628152 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3453.628152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	95955593377486767126381337239959810898366075266215546939497707180053069256785	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	88571994091116277621683333244266759807876252572103696436260986155203969667798	303	UVM_ERROR @ 2658.942760 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 2658.942760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				1 test run
	chip_sw_pwrmgr_sleep_power_glitch_reset	69035477036540493400534009926341085489798566765983354481725545623832238330610	313	UVM_ERROR @ 3174.151786 us: (rom_ctrl.sv:590) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3174.151786 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	45615544076041460702285270296967426711949099071609471306714849848954783893438	332	UVM_INFO @ 34623.680732 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:372)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	106911421019869494765076515708721728690023963505232122956733248954054402301361	307	UVM_INFO @ 3401.543650 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	101658411625563062664134885005789237253988565217250557694845065380110234463577	308	UVM_INFO @ 3376.070575 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	103680287137543941701427281614504397381771422769029775618549769271266437859852	None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				1 test run
	chip_tl_errors	34539299886695599262323259600943502219087210729195002885769892344141471415464	218	TL item was: req: (cip_tl_seq_item@175582) { a_addr: 'h10438 a_data: 'ha0dda5f4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h8 a_opcode: 'h4 a_user: 'h1bd78 d_param: 'h0 d_source: 'h8 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 3117.232890 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	25587785868421842052043978495614763115742058319736561656684273981257607026966	343	UVM_INFO @ 3188.183251 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.				1 test run
	chip_sw_rv_dm_access_after_wakeup	22108708844107531128844835763675605234169128127546560026883108171235515491985	329	UVM_INFO @ 13227.919208 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	100438276985760379165376866255841989458040930736869335785368217375022906871625	256	UVM_INFO @ 5650.249800 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_idle_load	93092528626926516918502534510466460471305932112851378669254723922936365957609	318	UVM_INFO @ 14164.366620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_sleep_load	62815507810594285635436360938114145065287446877131472827476945616647072128525	337	UVM_INFO @ 14757.345450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	87819653370736085130846595111018364105686033247053664681617185082976906952763	327	UVM_INFO @ 10526.518028 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	68112749214318041903750265607453737825908122561816754687773361009827536295352	272	UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:--*				1 test run
	rom_e2e_shutdown_exception_c	10908779710052650020276719200337988950045115806821418952434523470260804827783	319	" == "OpenTitan:4001-0002-01 " UVM_INFO @ 5334.626979 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:--*				1 test run
	rom_e2e_shutdown_output	103287091950118284872431124570221928594774397500256196550907264099708330002081	312	" == "OpenTitan:4001-0002-01 " UVM_INFO @ 6308.467801 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	115498935567598082354978892717399491301379750032461303070443455166483257503326	325	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	65298196916797221779324797010746582149835117085566116537811545210999421404098	327	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds				1 test run
	rom_e2e_jtag_debug_test_unlocked0	21366044017416895423692139007570453131901297611465048243535960894584095782529	318	UVM_INFO @ 5122.689967 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_no_meas	63412837658836608107373976961482977198865549245281563795224658733952486002078	319	UVM_INFO @ 16033.223467 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_invalid_meas	61010453911458892935123901312438883660218894425096457615928561211052596130276	319	UVM_INFO @ 16671.850325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	17528142240868008226881930200535519820983517934662779227461844867377954414818	327	UVM_ERROR @ 4064.692755 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4064.692755 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---