Simulation Results: clkmgr

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.66 %
  • code
  • 98.06 %
  • assert
  • 95.20 %
  • func
  • 84.73 %
  • line
  • 98.97 %
  • branch
  • 98.43 %
  • cond
  • 93.69 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.800s 16.949us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.790s 52.161us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.780s 15.498us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 14.630s 5700.733us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.990s 57.042us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.090s 91.443us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.780s 15.498us 1 1 100.00
clkmgr_csr_aliasing 0.990s 57.042us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.730s 40.410us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.830s 19.654us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.800s 40.376us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.670s 19.742us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.800s 16.949us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 7.340s 2506.150us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.610s 1243.015us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 7.340s 2506.150us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 1.540s 330.324us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.760s 37.524us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.980s 82.964us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.980s 82.964us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.790s 52.161us 1 1 100.00
clkmgr_csr_rw 0.780s 15.498us 1 1 100.00
clkmgr_csr_aliasing 0.990s 57.042us 1 1 100.00
clkmgr_same_csr_outstanding 1.140s 25.137us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.790s 52.161us 1 1 100.00
clkmgr_csr_rw 0.780s 15.498us 1 1 100.00
clkmgr_csr_aliasing 0.990s 57.042us 1 1 100.00
clkmgr_same_csr_outstanding 1.140s 25.137us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.730s 1.447us 0 1 0.00
clkmgr_tl_intg_err 1.430s 101.261us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 67.633us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 67.633us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 67.633us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 67.633us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.120s 94.602us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.430s 101.261us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 7.340s 2506.150us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.610s 1243.015us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.160s 67.633us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.680s 16.774us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.700s 18.170us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.820s 75.589us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.830s 28.646us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.750s 55.905us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.780s 15.498us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.730s 1.447us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.780s 15.498us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.780s 15.498us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.730s 1.447us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 2.130s 573.420us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 61.470s 12041.950us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1047) virtual_sequencer [clkmgr_common_vseq] Expected alert (fatal_fault) did not fire in * cycles. 1 test run
clkmgr_sec_cm 47029769706524765711982509777523278081083919218087245048257107957845822295909 78
UVM_INFO @ 1447353 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---