Simulation Results: edn/edn0

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.58 %
  • code
  • 77.62 %
  • assert
  • 94.36 %
  • func
  • 78.77 %
  • line
  • 96.52 %
  • branch
  • 88.42 %
  • cond
  • 84.45 %
  • toggle
  • 73.54 %
  • FSM
  • 45.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.870s 139.667us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.850s 18.929us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.750s 14.368us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 5.130s 643.891us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.080s 97.634us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.050s 28.730us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.750s 14.368us 1 1 100.00
edn_csr_aliasing 1.080s 97.634us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.890s 56.711us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.890s 56.711us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.890s 56.711us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.920s 22.237us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.030s 78.315us 1 1 100.00
errs 1 1 100.00
edn_err 0.960s 43.373us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 17.928us 1 1 100.00
edn_disable_auto_req_mode 1.180s 48.090us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.330s 236.361us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.740s 14.308us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.210s 77.582us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.190s 345.086us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.190s 345.086us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.850s 18.929us 1 1 100.00
edn_csr_rw 0.750s 14.368us 1 1 100.00
edn_csr_aliasing 1.080s 97.634us 1 1 100.00
edn_same_csr_outstanding 0.880s 23.710us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.850s 18.929us 1 1 100.00
edn_csr_rw 0.750s 14.368us 1 1 100.00
edn_csr_aliasing 1.080s 97.634us 1 1 100.00
edn_same_csr_outstanding 0.880s 23.710us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.550s 628.272us 1 1 100.00
edn_tl_intg_err 1.450s 107.582us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.060s 229.812us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.030s 78.315us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.550s 628.272us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.550s 628.272us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.550s 628.272us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.550s 628.272us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.030s 78.315us 1 1 100.00
edn_sec_cm 6.550s 628.272us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.030s 78.315us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.450s 107.582us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 25.650s 3329.112us 1 1 100.00