Simulation Results: entropy_src/rng_4bits

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.47 %
  • code
  • 86.09 %
  • assert
  • 83.25 %
  • func
  • 51.06 %
  • block
  • 94.17 %
  • line
  • 96.89 %
  • branch
  • 85.87 %
  • toggle
  • 76.20 %
  • FSM
  • 85.42 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 26.951us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 30.397us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 1.000s 119.848us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 12.000s 3664.843us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 102.278us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 2.000s 10.941us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 1.000s 119.848us 1 1 100.00
entropy_src_csr_aliasing 3.000s 102.278us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 26.951us 1 1 100.00
entropy_src_rng 199.000s 14062.239us 1 1 100.00
entropy_src_fw_ov 12.000s 14470.051us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 12.000s 14470.051us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 199.000s 14062.239us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 94.000s 14052.480us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 199.000s 14062.239us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 199.000s 14062.239us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 199.000s 14062.239us 1 1 100.00
entropy_src_intr 2.000s 60.747us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 199.000s 14062.239us 1 1 100.00
entropy_src_functional_alerts 4.000s 725.973us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 100.000s 14220.782us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 2.000s 93.628us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 81.279us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 2.000s 22.057us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 49.195us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 47.792us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 47.792us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 30.397us 1 1 100.00
entropy_src_csr_rw 1.000s 119.848us 1 1 100.00
entropy_src_csr_aliasing 3.000s 102.278us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 138.834us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 30.397us 1 1 100.00
entropy_src_csr_rw 1.000s 119.848us 1 1 100.00
entropy_src_csr_aliasing 3.000s 102.278us 1 1 100.00
entropy_src_same_csr_outstanding 3.000s 138.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 70.357us 1 1 100.00
entropy_src_tl_intg_err 3.000s 140.365us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 199.000s 14062.239us 1 1 100.00
entropy_src_cfg_regwen 1.000s 16.266us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 199.000s 14062.239us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 199.000s 14062.239us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 199.000s 14062.239us 1 1 100.00
entropy_src_fw_ov 12.000s 14470.051us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 93.628us 1 1 100.00
entropy_src_sec_cm 2.000s 70.357us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 2.000s 93.628us 1 1 100.00
entropy_src_sec_cm 2.000s 70.357us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 199.000s 14062.239us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 93.628us 1 1 100.00
entropy_src_sec_cm 2.000s 70.357us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 2.000s 93.628us 1 1 100.00
entropy_src_sec_cm 2.000s 70.357us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 2.000s 93.628us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 4.000s 725.973us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 140.365us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 117.000s 14179.030us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 11.000s 2918.585us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 98466870175766483126402473292383945929686021861977853731138188188546892484759 121
UVM_INFO @ 2918585003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror adaptp_lo_total_fails 1 test run
entropy_src_csr_mem_rw_with_rand_reset 88867049214824734125171924719377300599234468689497713840756244947578813486964 113
UVM_INFO @ 10941334 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---