Simulation Results: flash_ctrl

 
16/07/2026 15:30:28 DVSim: v1.49.12 sha: f3c0267 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.48 %
  • code
  • 93.95 %
  • assert
  • 96.77 %
  • func
  • 95.73 %
  • line
  • 95.96 %
  • branch
  • 97.12 %
  • cond
  • 93.80 %
  • toggle
  • 95.82 %
  • FSM
  • 87.07 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 45.210s 164.237us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 13.020s 34.086us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 20.220s 33.343us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.670s 79.103us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 25.250s 1905.705us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 30.500s 1686.171us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 8.470s 38.329us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.670s 79.103us 1 1 100.00
flash_ctrl_csr_aliasing 30.500s 1686.171us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.540s 122.253us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.970s 31.631us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 15.400s 41.152us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 11.490s 40.193us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1142.250s 171127.050us 1 1 100.00
flash_ctrl_hw_rma_reset 608.180s 760554.469us 1 1 100.00
flash_ctrl_lcmgr_intg 8.160s 158.001us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 977.080s 304361.347us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 217.960s 10839.618us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.150s 45.011us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1729.760s 104908.776us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 51.780s 1494.501us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 21.520s 40.180us 1 1 100.00
flash_ctrl_rw_evict_all_en 16.390s 88.291us 1 1 100.00
flash_ctrl_re_evict 16.890s 264.436us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 111.650s 435.843us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 111.650s 435.843us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 86.020s 5756.419us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 11.990s 528.991us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 137.640s 723.992us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 371.200s 2059.596us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 382.760s 2190.105us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 951.230s 2039.025us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.240s 42.520us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 113.540s 1347.953us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.110s 63.912us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.770s 30.059us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 362.070s 246.761us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 72.220s 8017.013us 1 1 100.00
flash_ctrl_otp_reset 49.430s 99.380us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1142.250s 171127.050us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 80.900s 3367.298us 1 1 100.00
flash_ctrl_intr_wr 43.560s 2551.858us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 164.740s 12007.831us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 110.120s 65385.003us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 40.140s 2124.885us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 36.410s 2084.489us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 13.670s 135.859us 1 1 100.00
flash_ctrl_ro_derr 117.080s 1222.231us 1 1 100.00
flash_ctrl_rw_derr 142.370s 2344.573us 1 1 100.00
flash_ctrl_derr_detect 92.400s 2155.082us 1 1 100.00
flash_ctrl_integrity 284.130s 15060.742us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 13.190s 122.908us 1 1 100.00
flash_ctrl_ro_serr 97.290s 1987.189us 1 1 100.00
flash_ctrl_rw_serr 142.650s 11868.810us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 50.020s 8991.482us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 53.220s 1029.768us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 116.230s 21977.423us 1 1 100.00
flash_ctrl_write_word_sweep 6.980s 54.533us 1 1 100.00
flash_ctrl_read_word_sweep 9.010s 54.978us 1 1 100.00
flash_ctrl_ro 96.380s 3121.527us 1 1 100.00
flash_ctrl_rw 369.340s 4244.776us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 19.640s 350.358us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 543.170s 41396.973us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 50.210s 10028.059us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.170s 64.700us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.930s 90.395us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 11.730s 226.179us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 11.730s 226.179us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.220s 33.343us 1 1 100.00
flash_ctrl_csr_rw 8.670s 79.103us 1 1 100.00
flash_ctrl_csr_aliasing 30.500s 1686.171us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.780s 745.936us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 20.220s 33.343us 1 1 100.00
flash_ctrl_csr_rw 8.670s 79.103us 1 1 100.00
flash_ctrl_csr_aliasing 30.500s 1686.171us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.780s 745.936us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 35.510s 221.127us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 35.510s 221.127us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 35.510s 221.127us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 35.510s 221.127us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 18.540s 88.022us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1758.150s 1973.928us 1 1 100.00
flash_ctrl_tl_intg_err 165.180s 673.405us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 165.180s 673.405us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 165.180s 673.405us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.240s 72.639us 1 1 100.00
flash_ctrl_wr_intg 7.760s 178.956us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 45.210s 164.237us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 49.430s 99.380us 1 1 100.00
flash_ctrl_disable 10.110s 63.912us 1 1 100.00
flash_ctrl_sec_info_access 44.270s 2530.934us 1 1 100.00
flash_ctrl_connect 7.770s 30.059us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 7.100s 27.542us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.670s 79.103us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 35.510s 221.127us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.670s 79.103us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 35.510s 221.127us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.670s 79.103us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 35.510s 221.127us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.110s 63.912us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.240s 72.639us 1 1 100.00
flash_ctrl_access_after_disable 7.840s 140.531us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 15.260s 28.126us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.110s 63.912us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 11.990s 528.991us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 369.340s 4244.776us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 142.650s 11868.810us 1 1 100.00
flash_ctrl_rw_derr 142.370s 2344.573us 1 1 100.00
flash_ctrl_integrity 284.130s 15060.742us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1142.250s 171127.050us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.150s 1973.928us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.150s 1973.928us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.150s 1973.928us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1758.150s 1973.928us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 12.930s 880.858us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 8.670s 86.011us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 7.240s 23.420us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1758.150s 1973.928us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.150s 1973.928us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1758.150s 1973.928us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 23.260s 85.858us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 388.250s 8655.373us 1 1 100.00